Texas Instruments TMS320C6201 manual CPU L2-unit Long Instructions Corrupted During Interrupt

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TMS320C6201 Silicon Errata

SPRZ153

Alternate Workaround:

Resolution

Advisory 3.0.9

Revision(s) Affected: Details:

Workaround:

Resolution

EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued)

The following alternate workarounds can help for certain board and layout configurations.

•Using faster (125 MHz or PC100) SDRAMs and/or SBSRAMs will reduce the chances of data corruption and/or increase the frequency at which reliable memory operation can be observed. Operation is not specified to be reliable across operating conditions and different samples of memory and C6201B devices due to lot-to-lot variation on both the memory and the C6201B.

•SDCLK/SSCLK can be delayed externally. This can be accomplished either via inverter(s), precision delay device, or longer board route on the clock line. The idea is to force the external clock to resemble the desired clock waveform as closely as possible, providing more setup for both reads and writes.

•You may start the device at a frequency where the skew does not occur and raise the operating frequency to the desired rate. This must be done at each processor reset. This solution works since the speedpath exists in the reset (non-run time) operation of the SDCLK/SSCLK circuit. Whatever operations starts at reset is observable until the next reset.

•Revision 3.1 of silicon will correct this problem.

CPU: L2-unit Long Instructions Corrupted During Interrupt

3.0, 2.1, and 2.0

If an interrupt occurs causing a B-side L-unit (.L2 unit) instruction that writes a long value to be annulled, the top 8 bits of the result will be written rather than being annulled. This bug only applies to the B-side L-unit (.L2 unit). The A-side L-unit (.L1 unit) functions correctly. (Internal reference number C620774)

This bug will not affect:

•Customers programming in C with no long data types.

•Customers not using code with long instructions on the .L2-unit.

•Customers only using long instructions on the .L2-unit inside loops 5 or less than 5 cycles long. (Interrupts are disabled in the five delay slots of a branch.)

•Disable interrupts using the appropriate compiler switches or register modifications in the affected C code.

•Disable interrupts seven execute packets before any long instructions on the .L2-unit that are not in the delay slots of a branch.

•Use the .L1-unit for long instructions if interrupts are anticipated.

•Revision 3.1 of silicon will correct this problem.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing DMA Channel 0 Multiframe Split-Mode Incompletion Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode Emif RBTR8 Bit Not FunctionalFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Emif Data Setup Times Documentation SupportImportant Notice
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