Texas Instruments TMS320C6201 manual Introduction

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TMS320C6201 Silicon Errata

SPRZ153

1 Introduction

This document describes the silicon updates to the functional specifications for the TMS320C6201 silicon releases 3.1, 3.0, 2.1, and 2.0.

1.1Quality and Reliability Conditions

TMX Definition

Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) product reliability for products classified as “TMX.” By definition, the product has not completed data sheet verification or reliability performance qualification according to TI Quality Systems Specifications.

The mere fact that a “TMX” device was tested over a particular temperature and voltage ranges should not, in any way, be construed as a warranty of performance.

TMP Definition

TI does not warranty product reliability for products classified as “TMP.” By definition, the product has not completed reliability performance qualification according to TI Quality Systems Specifications; however, products are tested to a published electrical and mechanical specification.

TMS Definition Fully-qualified production device.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing Timer Clock Output Not Driven for External Clock Power-Down Pin PD Not Set High for Power-Down 2 ModeDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalMcBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overEmif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Emif Data Setup Times Documentation SupportImportant Notice