Texas Instruments TMS320C6201 manual Pmemc Branch from External to Internal

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.1.19

Revision(s) Affected:

Details:

Workaround:

PMEMC: Branch from External to Internal

2.1 and 2.0

The program flow is corrupted after branching from external memory to internal program memory when the following are true:

•CPU is executing from external memory

•A CPU stall occurs that holds the CPU until all pending program fetches complete. CPU stalls may be caused by:

–External data access

–Multicycle NOPs

–Prolonged data memory bank conflict with DMA

–Multiple accesses to on-chip peripherals (not likely to cause this problem)

•A branch to internal program memory is taken before a new fetch packet is requested (i.e. during the same fetch packet that is executed when the CPU stalls.

The CPU will branch correctly to the internal memory location and correctly execute the code located there. When the branch is executed to return to external memory, the CPU will not complete the branch properly and the program will crash. (Internal reference number 0958)

There are several workaround options, depending on the situation that causes the failure. One or more of the following should be used to circumvent the problem:

•If the problem arises during an interrupt, move IST to external memory (same CE as code).

•If the problem occurs after a branch, delay the branch instruction with single-cycle NOPs or extend the delay slots to span multiple fetch packets (i.e., follow the branch instruction with parallel NOPs).

•If an external data access is causing the CPU stall, place data in internal data memory.

•If a multicycle NOP is causing the stall, change to multiple single-cycle NOPs.

•If the stall is due to the CPU being starved, change the DMA priority to be lower than that of the CPU.

Advisory 2.1.21

Revision(s) Affected:

Details:

Workaround:

DMA: DMA Data Block Corrupted After Start Zero Transfer Count

2.1 and 2.0

If DMA is stopped after it has been started with a zero transfer count, then reprogrammed and started again, the first element of the block will be corrupted. (Internal reference number 0242)

Make sure the transfer count is not near zero when starting the DMA.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Emif RBTR8 Bit Not Functional Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode DMA Channel 0 Multiframe Split-Mode IncompletionFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Documentation Support Emif Data Setup TimesImportant Notice
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