TMS320C6201 Silicon Errata | SPRZ153 |
Advisory 2.0.19
Revision(s) Affected:
Details:
Workaround:
EMIF: Data Setup Times
2.0
The data setup time for the external memory interface is listed in the February 21, 1998 Advanced Information TMSX320C6201 Data Sheet as 2 ns, 3 ns, and 2 ns for
In room temperature operation, we have not seen these setup times affect operation except in the case of SDRAM where it may be limited to
Advisory 2.0.24
Revision(s) Affected:
Details:
Workaround:
EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur
2.0
If a trickle refresh is waiting for the EMIF, and the refresh timer counts down and makes the refresh urgent just as the EMIF grants the request, then CE is held low for only 1/2 SDCLK cycle during the deactivate command before the refresh. This will result in an invalid deactivate command. Since the SDRAM did not deactivate the open page, the next activate command following the refresh will not be executed by the SDRAM. This will cause any subsequent accesses to go to the
Increase the refresh period.
7 Documentation Support
For
To access documentation on the web site:
1.Go to http://www.ti.com
2.Open the “Products” dialog box and choose “Digital Signal Processors”
3.Scroll to the “TMS320C6000tHighest Performance DSP Platform” and click on “TMS320C62x DSP Generation”.
4.Click on a device name and then click on the documentation type you prefer.
TMS320C6000 and C62x are trademarks of Texas Instruments.
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