Texas Instruments TMS320C6201 manual Documentation Support, Emif Data Setup Times

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.0.19

Revision(s) Affected:

Details:

Workaround:

EMIF: Data Setup Times

2.0

The data setup time for the external memory interface is listed in the February 21, 1998 Advanced Information TMSX320C6201 Data Sheet as 2 ns, 3 ns, and 2 ns for full-rate SBSRAM, half-rate SBSRAM, and SDRAM, respectively. In revision 2.0 of silicon, these values are to 4.8, 6.0, and 6.4 ns respectively, from worst-case simulation data (low voltage, high temperature, worst-case process conditions.)

In room temperature operation, we have not seen these setup times affect operation except in the case of SDRAM where it may be limited to 80–95 MHz.

Advisory 2.0.24

Revision(s) Affected:

Details:

Workaround:

EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur

2.0

If a trickle refresh is waiting for the EMIF, and the refresh timer counts down and makes the refresh urgent just as the EMIF grants the request, then CE is held low for only 1/2 SDCLK cycle during the deactivate command before the refresh. This will result in an invalid deactivate command. Since the SDRAM did not deactivate the open page, the next activate command following the refresh will not be executed by the SDRAM. This will cause any subsequent accesses to go to the non-deactivated page. This will cause corrupt data read and writes if the page to be opened after the refresh was not the same page that was open before the refresh. (Internal Reference Number 3453)

Increase the refresh period.

7 Documentation Support

For device-specific data sheets and related documentation, visit the TI web site at: http://www.ti.com.

To access documentation on the web site:

1.Go to http://www.ti.com

2.Open the “Products” dialog box and choose “Digital Signal Processors”

3.Scroll to the “TMS320C6000tHighest Performance DSP Platform” and click on “TMS320C62x DSP Generation”.

4.Click on a device name and then click on the documentation type you prefer.

TMS320C6000 and C62x are trademarks of Texas Instruments.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing Timer Clock Output Not Driven for External Clock Power-Down Pin PD Not Set High for Power-Down 2 ModeDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalMcBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overEmif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Emif Data Setup Times Documentation SupportImportant Notice
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