Texas Instruments manual TMS320C6201 Silicon Errata

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.1.19 PMEMC: Branch from External to Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Advisory 2.1.21 DMA: DMA Data Block Corrupted After Start Zero Transfer Count . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Advisory 2.0.1 Program Fetch: Cache Modes Not Functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Advisory 2.0.2 Bootload: Boot from 16-Bit and 32-Bit Asynchronous ROMs Not Functional . . . . . . . . . . . . . . . . . . 24

Advisory 2.0.3 DMA Channel 0 Split Mode Combined With autoinitialization Performs Improper

Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Advisory 2.0.4 DMA/Program Fetch: Cannot DMA into Program Memory From External . . . . . . . . . . . . . . . . . . . . 24

Advisory 2.0.5 Data Access: Parallel Accesses to EMIF or Internal Peripheral Bus Location

Sequenced Wrong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Advisory 2.0.7 EMIF: Reserved Fields Have Incorrect Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Advisory 2.0.8 EMIF: SDRAM Refresh/DCAB Not Performed Prior to HOLD Request Being Granted . . . . . . . . . 25 Advisory 2.0.9 McBSP New Block Interrupt Does Not Occur for Start of Block 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Advisory 2.0.11 DMA/Internal Data Memory: First Load Data Corrupted When DMA in High Priority . . . . . . . . . . . 26 Advisory 2.0.12 McBSP: FRST Improved in 2.1 over 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Advisory 2.0.13 McBSP: XEMPTY Stays Low When DXR Written Late . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Advisory 2.0.14 EMIF: Multiple SDRAM CE Spaces: Invalid Access After Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Advisory 2.0.18 DMA/Internal Data Memory: Conflict Data Corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Advisory 2.0.19 EMIF: Data Setup Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Advisory 2.0.24 EMIF Extremely Rare Cases Cause an Improper Refresh Cycle to Occur . . . . . . . . . . . . . . . . . . . . 28

7 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncEmif Invalid Sdram Access to Last 1K Byte of CE3 DMA Paused During Emulation HaltDMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Emif RBTR8 Bit Not Functional Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode DMA Channel 0 Multiframe Split-Mode IncompletionEmif Hold Feature Improvement on Revision McBSP Incorrect mLaw Companding ValueFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshBootload HPI Feature Improvement on Revision DMA Split-mode Receive Transfer Incomplete After PauseDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockMcBSP Xempty Stays Low When DXR Written Late Emif Multiple Sdram CE Spaces Invalid Access After RefreshDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice
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