Texas Instruments TMS320C6201 manual Advisory, Issues When Pausing at a Block Boundary

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TMS320C6201 Silicon Errata

SPRZ153

3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications

Advisory 3.1.1

Revision(s) Affected:

Details:

Workaround:

Issues When Pausing at a Block Boundary

3.1, 3.0, 2.1, and 2.0

The following problems exist when a DMA channel is paused at a block boundary:

•DMA does not flush internal FIFO when a channel is paused across block boundary. As a result, data from old and new blocks of that channel are in FIFO simultaneously. This prevents other channels from using the FIFO for high performance until that channel is restarted. Data is not lost when that channel is started again. (Internal reference number C601299)

•For DMA transfers with autoinitialization, if a channel is paused just as the last transfer in a block completes (just as the transfer counter reaches zero), none of the register reloads take place (count, source address, and destination address). When the same channel is restarted, the channel will not transfer anything due to the zero transfer count. This problem only occurs at block boundaries. (Internal reference number C601258)

Do not pause across block boundary if the internal FIFO is to be used by other channels for high performance. For DMA transfers with autoinitialization, if a channel is paused with a zero transfer count, manually reload all registers before restarting the channel.

Advisory 3.1.2

Revision(s) Affected:

Details:

Workaround:

DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame

3.1, 3.0, 2.1, and 2.0

If a frame-synchronized transfer is paused in mid-frame and then restarted again, a DMA channel does not continue the transfer. Instead, the channel waits for synchronization. If the channel is manually synchronized, it will properly complete the frame, but will immediately begin the transfer of the next frame. This behavior occurs for both a software pause (setting START = 10b) and for an emulation halt (with EMOD = 1). (Internal reference number C601257)

If pausing the DMA channel in software, do the following to restart:

1. Set the RSYNC bit in the Secondary Control Register.

2. Read the Transfer Count Register and then write back to Transfer Count Register. This enables the present frame to transfer but will wait for the next sync event to trigger the next frame transfer.

3. Set START to 01b or 11b.

If pausing the DMA channel with an emulation halt, do the following to restart:

1. Double-click on the Transfer Count Register and hit enter (rewrite current transfer count).

2. Set the RSYNC STAT bit in the Secondary Control Register (change 0xXXXX4XXX to 0xXXXX1XXX).

3. Run.

NOTE: The sequence of 1 and 2 is critical for an emulator halt (EMOD = 1), but not for the software pause.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing Timer Clock Output Not Driven for External Clock Power-Down Pin PD Not Set High for Power-Down 2 ModeDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Emif Data Setup Times Documentation SupportImportant Notice
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