Texas Instruments TMS320C6201 manual Emif Reserved Fields Have Incorrect Values

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.0.5

Revision(s) Affected:

Details:

Workaround:

Advisory 2.0.7

Revision(s) Affected:

Details:

Workaround:

Data Access: Parallel Accesses to EMIF or Internal Peripheral Bus Location Sequenced Wrong

2.0

Parallel read and write accesses to the same EMIF or internal peripheral bus location are sequenced incorrectly when:

•A load and store are in the same execute packet and either

–The addresses both point to off-chip memory through the EMIF, and the load has a destination register in side A (therefore, the store would have a source register in side B). Or

–The addresses both point to the peripheral bus, and the load has a destination register in side B (therefore, the store would have a source register in side A).

When these conditions occur, the store occurs first rather than the load. In general, this will only cause an error if both the load and store addresses are the same. This bug does not occur if both accesses are to internal data memory. (Internal Reference Number 3087)

Avoid loading and storing the same address on the same cycle.

EMIF: Reserved Fields Have Incorrect Values

2.0

Fields in Bits 15:14 of the EMIF CE Space Control registers are writable. They should be read only and have a 0 value. Bits 5:4 of the EMIF SDRAM Control register are 11b rather than 0. (Internal Reference Number s 3248 and 3283)

Mask these values if 0s are expected and to only write 0s to reserved fields.

Advisory 2.0.8

Revision(s) Affected:

Details:

Workaround:

EMIF: SDRAM Refresh/DCAB Not Performed Prior to HOLD Request Being Granted

2.0

SDRAM is left in the current state when an external HOLD is granted. SDRAM refresh/DCAB is necessary if an interface to a shared memory external SDRAM controller is desired. (Internal Reference Number 3249)

Make sure the external controller performs a refresh/DCAB before performing SDRAM accesses.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncDMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Power-Down Pin PD Not Set High for Power-Down 2 Mode Timer Clock Output Not Driven for External ClockDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalMcBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshDMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockEmif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice
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