Texas Instruments TMS320C6201 manual DMA Channel 0 Multiframe Split-Mode Incompletion

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.1.7

DMA Channel 0 Multiframe Split-Mode Incompletion

Revision(s) Affected:

Details:

Workaround:

Advisory 2.1.8

Revision(s) Affected:

Details:

Workaround:

Advisory 2.1.9

Revision(s) Affected:

Details:

Workaround:

Advisory 2.1.10

Revision(s) Affected:

Details:

Workaround:

2.1 and 2.0

If DMA Channel 0 is configured to perform a multiframe split-mode transfer, it is possible for the last element of the last frame of the Receive Read to not be transferred. After the last element of the last frame of the Transmit Write Transfer, the element count is reloaded into the Channel 0 Transfer Counter Register, which may allow for the Transmit Read Transfer to be initiated. If the read synchronization and write synchronization are far enough apart in CPU cycles, then it is possible for the DMA to hang (due to the Transmit Read) before the Receive Write gets its sync event and completes the transmission. (Internal reference number 0558)

If a multiframe split-mode transfer is required, use DMA channel 1, 2, or 3.

Timer Clock Output Not Driven for External Clock

2.1 and 2.0

When FUNC = 1 (TOUT is a timer pin), if CLKSRC = 0 (external clock source), the TOUT pin is not driven with TSTAT. The timer still functions correctly, but the output is not seen externally. (Internal reference number 0568)

None. Timer functions correctly.

Power-Down Pin PD Not Set High for Power-Down 2 Mode

2.1 and 2.0

The power-down pin, PD, only goes high (active) in power-down mode 3, not in power-down mode 2. (Internal reference number 0537)

None. Power-down modes function correctly.

EMIF: RBTR8 Bit Not Functional

2.1 and 2.0

If RBTR8=1, a requester with continuous requests will not relinquish control of the EMIF even to a higher-priority requester. (Internal reference number 0432)

Leave RBTR8 set to the default of 0.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncDMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Emif RBTR8 Bit Not Functional Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode DMA Channel 0 Multiframe Split-Mode IncompletionMcBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshDMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockEmif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice
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