Texas Instruments TMS320C6201 manual Cache During Emulation With Extremely Slow External Memory

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 3.1.9

Revision(s) Affected:

Details:

Workaround:

Alternative: If a 64M-bit SDRAM is located in CE3, avoid using the last 1K byte in the CE3 memory map (0x03FFFC00).

Cache During Emulation With Extremely Slow External Memory

3.1, 3.0, 2.1, and 2.0

If a program requests fetch packet “A” followed immediately by fetch packet “B”, and all of the following four conditions are true:

1. A and B are separated by a multiple of 64K in memory (i.e., they will occupy the same cache frame)

2. B is currently located in cache

3. You are using the emulator to single-step through the branch from A to B

4. The code is running off of an extremely slow external memory that transfers one 32-bit word every 8000 or more CPU clock cycles (CPU running at 200 MHz)

Then A will be registered as a “miss” and B will be registered as a “hit”. B will not be reloaded into cache, and A will be executed twice. This condition is extremely rare because B has to be in cache memory, and must be the next fetch packet requested after A (which is not in cache memory). In addition, this problem only occurs if you single-step through the branch from A to B using the emulator, and if the code is located in an extremely slow external memory. (Internal reference number C630283)

•Do not single-step through the branch from A to B if the above conditions are true.

•Do not use an extremely slow external memory (transfers one 32-bit word every 8000 or more CPU clock cycles) if conditions 1, 2, and 3 are true.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Emif RBTR8 Bit Not Functional Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode DMA Channel 0 Multiframe Split-Mode IncompletionFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Documentation Support Emif Data Setup TimesImportant Notice