Texas Instruments TMS320C6201 manual Sbsram Write Timing 1/2 Rate Ssclk See Note

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TMS320C6201 Silicon Errata

SPRZ153

Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note)

SSCLK

1

CE

3

BE_ [3:0]

5

EA [21:2]

ED [31:0]

SSADS

SSOE

SSWE

BE1

A1

Q1

9

15

2

		4
BE2	BE3	BE4
		6
A2	A3	A4
13		14
Q2	Q3	Q4
		10

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NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since these timings are specified as minimums. However, the CE output setup and hold time may be greater than that shown

in the data sheet in multiples of P ns. In other words, for output setup time, the CEx transition from high to low may happen P, 2P, … , or nP ns before the time specified by the data sheet. Similarly, for output hold time, the CEx low-to-high transition may happen P, 2P, … , or nP ns after the time specified by the data sheet. This is indicated by the period of uncertainty for specs 1 and 2 in Figure 2, and Figure 3.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncDMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Emif RBTR8 Bit Not Functional Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode DMA Channel 0 Multiframe Split-Mode IncompletionMcBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshDMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockEmif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice