Texas Instruments TMS320C6201 manual DMA Rsync Cleared Late for Frame-synchronized Transfer

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TMS320C6201 Silicon Errata

SPRZ153

EMIF: SDRAM Invalid Access (Continued)

Workaround:Avoid use of multiple CE spaces of SDRAM within a single refresh period.

Advisory 2.1.4

Revision(s) Affected:

Workaround:

Advisory 2.1.5

Revision(s) Affected:

Details:

Workaround:

DMA: RSYNC Cleared Late for Frame-synchronized Transfer

2.1 and 2.0

In a frame-synchronized transfer, RSYNC is only cleared after the beginning of last write transfer. It should occur after the start of the first read transfer in the synchronized frame. (Internal reference number 0267)

Wait until end-of-frame (perhaps using DMAC pins for external status) to issue next frame synchronization.

McBSP: DXR to XSR Copy Not Generated

2.1 and 2.0

If any element size other than 32 bits is written to the DXR of either serial port, then the register is not copied to the XSR. (Internal reference number 0511)

The following workaround is applicable only for non-split mode DMA transfers.

1. For little-endian mode:

Always write 32 bits to the DXR. When using the DMA, it is possible to perform word transfers, but increment or decrement the address by one or two bytes using one of the global index registers. If the serial port is transferring out 16-bit words, which are stored on consecutive half-word boundaries in memory (either internal or external), the DMA would need to be set up such that it performs word writes to DXR (ESIZE = 00b). The global index register used would need an element index of 0x0002 (2 bytes). If an 8-bit data transfer is desired, then element index would need to be 0x0001.

Please note that this workaround assumes that the receive justification, RJUST in the McBSP’s SPCR is set for right justification (zero-fill or sign-extended). If left justification is chosen for receive data, the DMA receive src address pointing to DRR should be changed to DRR+3 (which is 0x018C0003 for McBSP0 and 0x01900003 for McBSP1) for byte-size elements and DRR+2 for half-word elements. This ensures packing data on byte or half-word boundaries for receive data.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing Timer Clock Output Not Driven for External Clock Power-Down Pin PD Not Set High for Power-Down 2 ModeDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalMcBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overEmif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Emif Data Setup Times Documentation SupportImportant Notice
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