Texas Instruments TMS320C6201 manual For big-endian mode

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TMS320C6201 Silicon Errata

SPRZ153

McBSP: DXR to XSR Copy Not Generated (Continued)

Example:

Configure the DMA as follows:

(a)For half-word/byte-size accesses with right justification on receive data:

ch_A: /* for transmit */

src_address = mem_out; dst_address = DXR;

Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 2 /* change this to 1 for byte writes */

ch_B : /* for receive */

src_address = DRR; dst_address = mem_in;

Element_size = HALF /* change this to BYTE for 8-b element size */Address_inc_mode = inc_by_ element_size

/* inc_by_index whose value is as specified for ch_A above will also work */

(b)For half-word / byte-size accesses with left justification on receive data:

Same as 1(a) above EXCEPT for:

ch_B : /* for receive */

src_address = DRR+3; /* for byte accesses */ OR = DRR+2; /* for half-word accesses */

2. For big-endian mode:

Always write 32 bits to the DXR.

(a)For half-word accesses with right justification on receive data:

ch_A: /* for transmit */ src_address = mem_out;

dst_address = DXR+2; /* 0x018C0006 for McBSP0 or 0x01900006 for McBSP1 */

Element_size = WORD Address_inc_mode = index Index_reg_value = 2

ch_B : /* for receive */

src_address = DRR+2 /* 0x018C0002 for McBSP0 or 0x01900002 for McBSP1 */ dst_address = mem_in;

Element_size = HALF;

Address_inc_mode = = inc_by_ element_size

/* inc_by_index whose value is as specified for ch_A above will also work */

(b)For half-word writes with left justification on receive data:

Same as 2(a) above EXCEPT for: ch_B : /* for receive */ src_address = DRR;

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Power-Down Pin PD Not Set High for Power-Down 2 Mode Timer Clock Output Not Driven for External ClockDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Documentation Support Emif Data Setup TimesImportant Notice