Texas Instruments TMS320C6201 manual McBSP Incorrect mLaw Companding Value

Page 20

TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.1.11

Revision(s) Affected:

Details:

McBSP: Incorrect mLaw Companding Value

2.1 and 2.0

The C6201 McBSP m-Law/A-Law companding hardware produces an incorrectly expanded m-Law value. McBSP receives m-Law value 0111 1111, representing a mid-scale analog value. Expanded 16-bit data is 1000 0000 0000 0000, representing a most negative value. Expected value is 0000 0000 0000 0000. McBSP expands ∝ -Law 1111 1111 (also mid-scale value) correctly. m-Law works correctly for all encoded values, except for 0x7f. (Internal Reference Number 0651)

Advisory 2.1.12

Revision(s) Affected:

Details:

Workaround:

Advisory 2.1.13

Revision(s) Affected:

Details:

Workaround:

False Cache Hit – Extremely Rare

2.1 and 2.0

If a program requests fetch packet “A” followed immediately by fetch packet “B”, and the following are true:

•A and B are separated by a multiple of 64K in memory (i.e., they will occupy the same cache frame)

•B is currently located in cache

Then, A will be registered as a “miss” and B will be registered as a “hit”. B will not be reloaded into cache, and A will be executed twice. This condition is extremely rare because B has to be in cache memory, and must be the next fetch packet requested after A (which is not in cache memory). (Internal Reference Number 4372)

The program should be relinked to force A and B to not be a multiple of 64K apart.

EMIF: HOLD Feature Improvement on Revision 3

2.1 and 2.0

This is documented as a difference between the TMX320C6201 revision 2.x (and earlier) and revision 3.0 (and later).

The HOLD feature of the C6201 currently will not respond to a HOLD request if the NOHOLD bit is set at the time of the HOLD request, but is then cleared while the HOLD request is pending. In other words, for a HOLD request to be recognized, a high-to-low transition must occur on the HOLD input while the NOHOLD bit is not set. Future revisions of the device will operate as described below.

If NOHOLD is set and a HOLD request comes in, the C62xt will ignore the HOLD request. If while the HOLD request is still asserted the NOHOLD bit is then deasserted, the HOLD will be acknowledged as expected. (Internal reference number 0101)

To recognize a pending HOLD request when the state of the NOHOLD bit is changed from 1 to 0, a pulse must be generated on the input HOLD line. This can be done by logically OR-ing a normally low general-purpose output (DMAC can be used) with the HOLD request signal from the requester, and creating a high pulse on the general-purpose output pin.

20

Page 19 Page 21
Image 20
Page 19 Page 21
Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing Timer Clock Output Not Driven for External Clock Power-Down Pin PD Not Set High for Power-Down 2 ModeDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Emif Data Setup Times Documentation SupportImportant Notice
Top Page Image Contents