Texas Instruments TMS320C6201 manual Emif Hold Request Causes Problems With Sdram Refresh

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.1.14

Revision(s) Affected:

Details:

Workaround:

EMIF: HOLD Request Causes Problems With SDRAM Refresh

2.1 and 2.0

If the HOLD interface is used in a system with SDRAM, there are some situations that are likely to occur.

If the NOHOLD bit is not set and an external requester attempts to gain control of the bus via the HOLD signal of the EMIF at the exact same time when the EMIF is issuing a SDRAM Refresh command, the HOLD request is never recognized. Even if the NOHOLD bit is set in the EMIF Global Control Register, SDRAM refreshes are still disabled as long as the HOLD request is pending. A single refresh after receiving the HOLD request is issued, but no additional refreshes are issued until the HOLD request is removed. The C62xt still owns the bus since the NOHOLD bit is set.

In addition, if an SDRAM burst is started just prior to a HOLD request, it is possible that the request will not be recognized until a refresh occurs. This will potentially allow for the HOLD request to be ignored for several microseconds. (Internal reference number 0757 and 0777)

Do not allow a requester to activate the HOLD line without acknowledging it for longer than the SDRAM refresh period. A workaround can be accomplished by keeping the NOHOLD bit set and software-polling the HOLD bit of the EMIF Global Control Register. Software-polling of the HOLD bit in the EMIF Global Control Register will indicate when a HOLD request has been received (this can be done in the SD_INT service routine or Timer interrupt service routine).

Upon detecting a HOLD request, SDRAM refreshes are disabled, NOHOLD bit is cleared, and a pulse is generated on the input HOLD signal (can use DMACx as a general-purpose output pin in combination with the requesters HOLD signal). Then, NOHOLD can be set and SDRAM refreshes enabled in anticipation of the next HOLD request.

Advisory 2.1.15

Revision(s) Affected:

Details:

Workaround:

DMA Priority Ignored by PBUS

2.1 and 2.0

The CPU always has priority over the DMA when accessing peripherals. The DMA PRI bit is ignored and treated as “0”. (Internal reference number 0540)

Leave sufficient gaps in CPU accesses to the PBUS to allow the DMA time to gain adequate access.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncEmif Invalid Sdram Access to Last 1K Byte of CE3 DMA Paused During Emulation HaltDMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Power-Down Pin PD Not Set High for Power-Down 2 Mode Timer Clock Output Not Driven for External ClockDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalEmif Hold Feature Improvement on Revision McBSP Incorrect mLaw Companding ValueFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshBootload HPI Feature Improvement on Revision DMA Split-mode Receive Transfer Incomplete After PauseDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockMcBSP Xempty Stays Low When DXR Written Late Emif Multiple Sdram CE Spaces Invalid Access After RefreshDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice
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