Texas Instruments TMS320C6201 manual McBSP New Block Interrupt Does Not Occur for Start of Block

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.0.9

Revision(s) Affected:

Details:

Workaround:

Advisory 2.0.11

Revision(s) Affected:

Details:

Workaround:

Advisory 2.0.12

Revision(s) Affected:

Details:

McBSP New Block Interrupt Does Not Occur for Start of Block 0

2.0

When end-of-block interrupt is selected ((R/X)INTM=01b), McBSP new block interrupt does not occur at end of frame (i.e., before block 0). (Internal reference number 4357)

This interrupt is used when on-the-fly channel selection/enabling is being performed. A static channel selection/enabling avoids this.

DMA/Internal Data Memory: First Load Data Corrupted When DMA in High Priority

2.0

In the case of a single load from A side or B side followed by two loads in parallel from both sides, and in concert with a DMA high-priority access to the same bank as the parallel load, the DMEMC provides corrupt data for that first load. (Internal Reference Number 3858)

Example:

LDW

.D1

*A3, A4; A4 gets corrupt data due to the bug

 

LDW

.D2

*B3, B4

 

LDW

.D1

*A6, A7

Avoid high-priority DMA transfers to/from internal data memory during these conditions.

McBSP: FRST Improved in 2.1 over 2.0

2.0

The following enhancements were made in 2.1.

When FRST transitions to a 1, the first frame sync is generated after 8 CLKG clocks. The 2.0 implementation was such that the first frame sync was generated after FPER+1 number of CLKG clocks.

FRST = 1 is valid only when GRST = 1. In other words the user has to set FRST = 1 only after GRST = 1. If not, write to FRST = 1 is ignored or rather a zero is forced on FRST by the logic.

During normal operation, when FRST = 1 and GRST = 1, and now the user puts the sample rate generator in reset (GRST=0) without first clearing the FRST bit to zero, then the logic will force a zero to the FRST bit before shutting down the sample-rate generator.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing DMA Channel 0 Multiframe Split-Mode Incompletion Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode Emif RBTR8 Bit Not FunctionalFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Emif Data Setup Times Documentation SupportImportant Notice
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