Texas Instruments TMS320C6201 manual Emif CE Space Crossing on Continuous Request Not Allowed

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TMS320C6201 Silicon Errata

SPRZ153

5 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications

Advisory 2.1.1

Revision(s) Affected:

Details:

Workaround:

EMIF: CE Space Crossing on Continuous Request Not Allowed

2.1 and 2.0

Any continuous request of the EMIF cannot cross CE address space boundaries. This condition can result in bad data read, or writing to the wrong CE. (Internal Reference Numbers 2600 and 3421)

CPU Program Fetch: The simplest fix is for all external program to reside within a single CE space. Alternatively, program fetch flow should not occur across CE spaces. This can be accomplished by branching on-chip between executing from one CE to another CE.

DMA: All DMA block transfers without read or write synchronization should have all EMIF addresses within a frame to belong to one CE space. In other words, all read (src) addresses should belong to one CE space and should not cross CE boundaries. The same applies to write (dst) addresses within a frame. Note that the source can be in the same CE space or different CE space as the destination. DMA transfers with read and/or write synchronization together with CE boundaries crossed between frames are not affected by this bug.

CPU Data Access: External CPU data accesses cannot perform continuous requests and thus are not affected by this bug.

Advisory 2.1.2

Revision(s) Affected:

Details:

EMIF: SDRAM Invalid Access

2.1 and 2.0

An invalid SDRAM access occurs when all of the following are true:

•Two or more SDRAM devices in different CE spaces

•Each SDRAM device has a page activate

•One active page is in bank 0 and the other in bank 1

•Each CE space with SDRAM is accessed (alternating) without a page miss or refresh occurring (no Deactivate command).

OR

•Two or more SDRAM devices in different CE spaces

•A trickle refresh deactivates both devices

•Before refresh occurs, a request to access one CE space comes in. The refresh will wait until the first requester has completed.

•If request to second CE space occurs before refresh occurs, then an invalid access takes place, since the controller neglects the fact that this space was deactivated. (Internal Reference Numbers 4139, 0335, and 0871)

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncEmif Invalid Sdram Access to Last 1K Byte of CE3 DMA Paused During Emulation HaltDMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Emif RBTR8 Bit Not Functional Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode DMA Channel 0 Multiframe Split-Mode IncompletionEmif Hold Feature Improvement on Revision McBSP Incorrect mLaw Companding ValueFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshBootload HPI Feature Improvement on Revision DMA Split-mode Receive Transfer Incomplete After PauseDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockMcBSP Xempty Stays Low When DXR Written Late Emif Multiple Sdram CE Spaces Invalid Access After RefreshDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice
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