Texas Instruments TMS320C6201 manual Program Fetch Cache Modes Not Functional

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TMS320C6201 Silicon Errata

SPRZ153

6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications

Advisory 2.0.1

Revision(s) Affected:

Workaround:

Advisory 2.0.2

Revision(s) Affected:

Details:

Workaround:

Program Fetch: Cache Modes Not Functional

2.0

Use internal program memory in mapped mode.

Bootload: Boot from 16-Bit and 32-Bit Asynchronous ROMs Not Functional

2.0

16-bit-wide ROM mode and 32-bit-wide asynchronous mode work in run time without bugs. The problem is only in boot. (Internal Reference Number 3088)

Place all code in the lowest byte of the boot ROM.

Advisory 2.0.3

Revision(s) Affected:

Details:

Workaround:

Advisory 2.0.4

Revision(s) Affected:

Details:

Workaround:

DMA Channel 0 Split Mode Combined With autoinitialization Performs Improper Reinitialization

2.0

The source address (transmit read address) is reset too early when both split mode and autoinitialization are enabled. The bug exists on DMA channel 0 only. (Internal Reference Number 3481)

Substitute one of the other channels for channel 0 when this configuration is desired.

DMA/Program Fetch: Cannot DMA into Program Memory From External

2.0

Performing a DMA transfer into program memory while running from off-chip can cause invalid program data to read by the CPU. (Internal Reference Number 2978)

DMA into program memory only when running from internal program memory.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryEmif Invalid Sdram Access to Last 1K Byte of CE3 DMA Paused During Emulation HaltDMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing Timer Clock Output Not Driven for External Clock Power-Down Pin PD Not Set High for Power-Down 2 ModeDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalEmif Hold Feature Improvement on Revision McBSP Incorrect mLaw Companding ValueFalse Cache Hit Extremely Rare Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusBootload HPI Feature Improvement on Revision DMA Split-mode Receive Transfer Incomplete After PauseDMA Multiframe Transfer Data Lost During Stop Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overMcBSP Xempty Stays Low When DXR Written Late Emif Multiple Sdram CE Spaces Invalid Access After RefreshDMA/Internal Data Memory Conflict Data Corruption Emif Data Setup Times Documentation SupportImportant Notice