Texas Instruments TMS320C6201 manual Contents

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TMS320C6201 Silicon Errata

SPRZ153

 

Contents

1 Introduction

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1.1 Quality and Reliability Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TMX Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TMP Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TMS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Advisory 3.1.1 Issues When Pausing at a Block Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Advisory 3.1.2 DMA: Transfer Incomplete When Pausing a Synchronized Transfer in Mid-frame . . . . . . . . . . . . . . 8 Advisory 3.1.3 DMA Multiframe Split-mode Transfers Source Address Indexing Not Functional . . . . . . . . . . . . . . . 9 Advisory 3.1.4 DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Advisory 3.1.5 DMA Freezes if Postincrement/Decrement Across Port Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Advisory 3.1.6 DMA Paused During Emulation Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Advisory 3.1.7 DMA: RSYNC = 10000b (DSPINT) Does Not Wait for Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Advisory 3.1.8 EMIF: Invalid SDRAM Access to Last 1K Byte of CE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Advisory 3.1.9 Cache During Emulation With Extremely Slow External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Advisory 3.0.8 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Advisory 3.0.9 CPU: L2-unit Long Instructions Corrupted During Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Advisory 2.1.1 EMIF: CE Space Crossing on Continuous Request Not Allowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Advisory 2.1.2 EMIF: SDRAM Invalid Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Advisory 2.1.4 DMA: RSYNC Cleared Late for Frame-synchronized Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Advisory 2.1.5 McBSP: DXR to XSR Copy Not Generated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Advisory 2.1.6 DMA Split-mode End-of-frame Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Advisory 2.1.7 DMA Channel 0 Multiframe Split-Mode Incompletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.8 Timer Clock Output Not Driven for External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.9 Power-Down Pin PD Not Set High for Power-Down 2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.10 EMIF: RBTR8 Bit Not Functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Advisory 2.1.11 McBSP: Incorrect mLaw Companding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Advisory 2.1.12 False Cache Hit – Extremely Rare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Advisory 2.1.13 EMIF: HOLD Feature Improvement on Revision 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Advisory 2.1.14 EMIF: HOLD Request Causes Problems With SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Advisory 2.1.15 DMA Priority Ignored by PBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Advisory 2.1.16 DMA Split-mode Receive Transfer Incomplete After Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Advisory 2.1.17 DMA Multiframe Transfer Data Lost During Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Advisory 2.1.18 Bootload: HPI Feature Improvement on Revision 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Rsync = 10000b Dspint Does Not Wait for Sync Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Paused During Emulation Halt Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing DMA Channel 0 Multiframe Split-Mode Incompletion Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode Emif RBTR8 Bit Not FunctionalFalse Cache Hit Extremely Rare Emif Hold Feature Improvement on RevisionMcBSP Incorrect mLaw Companding Value Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Multiframe Transfer Data Lost During Stop Bootload HPI Feature Improvement on RevisionDMA Split-mode Receive Transfer Incomplete After Pause Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overDMA/Internal Data Memory Conflict Data Corruption McBSP Xempty Stays Low When DXR Written LateEmif Multiple Sdram CE Spaces Invalid Access After Refresh Emif Data Setup Times Documentation SupportImportant Notice