Texas Instruments TMS320C642X manual Start and Stop Conditions, Data Validity

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Peripheral Architecture

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2.4.2Data Validity

The data on SDA must be stable during the high period of the clock (see Figure 5). The high or low state of the data line, SDA, can change only when the clock signal on SCL is low.

Figure 5. Bit Transfer on the I2C-Bus

Data line

stable data

SDA

SCL

Change of data allowed

2.5START and STOP Conditions

The I2C peripheral can generate START and STOP conditions when the peripheral is configured to be a master on the I2C-bus, as shown in Figure 6:

•The START condition is defined as a high-to-low transition on the SDA line while SCL is high. A master drives this condition to indicate the start of a data transfer.

•The STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. A master drives this condition to indicate the end of a data transfer.

The I2C-bus is considered busy after a START condition and before a subsequent STOP condition. The bus busy (BB) bit of ICSTR is 1. The bus is considered free between a STOP condition and the next START condition. The BB is 0.

The master mode (MST) bit and the START condition (STT) bit in ICMDR must both be 1 for the I2C peripheral to start a data transfer with a START condition. The STOP condition (STP) bit must be set to 1 for the I2C peripheral to end a data transfer with a STOP condition. A repeated START condition generates when BB is set to 1 and STT is also set to 1. See Section 3.9 for a description of ICMDR (including the MST, STT, and STP bits).

Figure 6. I2C Peripheral START and STOP Conditions

SDA

SCL

START	STOP
condition (S)	condition (P)

12	Inter-Integrated Circuit (I2C) Peripheral	SPRUEN0D –March 2011
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementBus Structure Multiple I2C Modules ConnectedClocking Diagram for the I2C Peripheral Clock GenerationSignal Descriptions Clock SynchronizationInput and Output Voltage Levels Start and Stop Conditions Data ValiditySerial Data Formats 1 7-Bit Addressing FormatUsing a Repeated Start Condition 2 10-Bit Addressing FormatFree Data Format ACKOperating Mode Description Endianness ConsiderationsOperating Modes Operating Modes of the I2C PeripheralNack Bit Generation Ways to Generate a Nack BitNack Bit Generation I2C Peripheral Condition Basic OptionalArbitration Procedure Between Two Master-Transmitters ArbitrationReset Considerations Software Reset ConsiderationsHardware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description I2C Own Address Register Icoar I2C Own Address Register Icoar Field DescriptionsOaddr Bit Field Value DescriptionI2C Interrupt Mask Register Icimr I2C Interrupt Mask Register Icimr Field DescriptionsSCD Icxrdy Icrrdy Ardy Nack AASI2C Interrupt Status Register Icstr I2C Interrupt Status Register Icstr Field DescriptionsSdir Nacksnt Rsfull Xsmt SdirBit Field AD0An acknowledge bit ACK has been sent by the receiver I2C Clock Divider Registers Icclkl and Icclkh 1 I2C Clock Low-Time Divider Register Icclkl2 I2C Clock High-Time Divider Register Icclkh IcclI2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Data Receive Register Icdrr I2C Slave Address Register IcsarI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field DescriptionsI2C Mode Register Icmdr I2C Mode Register Icmdr Field DescriptionsRM bit is dont care Icmdr Bit Bus Activity DescriptionHow the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX Bit10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode 11 I2C Extended Mode Register Icemdr I2C Extended Mode Register Icemdr Field DescriptionsIgnack BCM R/W-0 R/W-1 Ignack12 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc 13 I2C Peripheral Identification Register ICPID1 14 I2C Peripheral Identification Register ICPID2Type I2CDocument Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid TI E2E Community Home