Texas Instruments TMS320C642X manual 2 10-Bit Addressing Format, Free Data Format, Ack

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Peripheral Architecture

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2.6.210-Bit Addressing Format

The 10-bit addressing format (Figure 9) is like the 7-bit addressing format, but the master sends the slave address in two separate byte transfers. The first byte consists of 11110b, the two MSBs of the 10-bit slave address, and R/W = 0 (write). The second byte is the remaining 8 bits of the 10-bit slave address. The slave must send acknowledgment (ACK) after each of the two byte transfers. Once the master has written the second byte to the slave, the master can either write data or use a repeated START condition to change the data direction. (For more information about using 10-bit addressing, see the Philips Semiconductors I2C-bus specification.)

Write 1 to the XA bit of ICMDR to select the 10-bit addressing format.

Figure 9. I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver

(FDF = 0, XA = 1 in ICMDR)

1

7

1

1

8

1

n

1

1

S

1 1 1 1 0 A A

0

ACK

A A A A A A A A

ACK

Data

ACK P

A A = 2 MSBs

R/W

8 LSBs of slave address

n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICMDR.

2.6.3Free Data Format

In the free data format (Figure 10), the first bits after a START condition (S) are a data word. An ACK bit is inserted after each data word, which can be from 1 to 8 bits, depending on the bit count (BC) bits of ICMDR. No address or data-direction bit is sent. Therefore, the transmitter and the receiver must both support the free data format, and the direction of the data must be constant throughout the transfer.

To select the free data format, write 1 to the free data format (FDF) bit of ICMDR.

Figure 10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR)

1

n

1

n

1

n

1

1

S

Data

ACK

Data

ACK

Data

ACK P

n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICMDR.

2.6.4Using a Repeated START Condition

The repeated START condition can be used with the 7-bit addressing, 10-bit addressing, and free data formats. The 7-bit addressing format using a repeated START condition (S) is shown in Figure 11. At the end of each data word, the master can drive another START condition. Using this capability, a master can transmit/receive any number of data words before driving a STOP condition. The length of a data word can be from 1 to 8 bits and is selected with the bit count (BC) bits of ICMDR.

Figure 11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition

(FDF = 0, XA = 0 in ICMDR)

1

7

1

1

n

1

1

7

1

1

n

1

1

S

Slave address

R/W

ACK

Data

ACK

S

Slave address

R/W

ACK

Data

ACK

P

1

Any

1

 

number

 

n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICMDR.

Any number

14

Inter-Integrated Circuit (I2C) Peripheral

SPRUEN0D –March 2011

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFeatures Not Supported Functional Block Diagram Industry Standards Compliance StatementBus Structure Multiple I2C Modules ConnectedClocking Diagram for the I2C Peripheral Clock GenerationInput and Output Voltage Levels Signal DescriptionsClock Synchronization Start and Stop Conditions Data ValiditySerial Data Formats 1 7-Bit Addressing FormatFree Data Format Using a Repeated Start Condition2 10-Bit Addressing Format ACKOperating Modes Operating Mode DescriptionEndianness Considerations Operating Modes of the I2C PeripheralNack Bit Generation Nack Bit GenerationWays to Generate a Nack Bit I2C Peripheral Condition Basic OptionalArbitration Procedure Between Two Master-Transmitters ArbitrationHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture DMA Events Generated by the I2C Peripheral Power ManagementInterrupt Support Acronym Register Description Emulation ConsiderationsInter-Integrated Circuit I2C Registers Oaddr I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions Bit Field Value DescriptionSCD Icxrdy Icrrdy Ardy Nack I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions AASSdir Nacksnt Rsfull Xsmt I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions SdirBit Field AD0An acknowledge bit ACK has been sent by the receiver 2 I2C Clock High-Time Divider Register Icclkh I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl IcclIcdc I2C Data Count Register IccntI2C Data Count Register Iccnt Field Descriptions I2C Data Receive Register Icdrr Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field DescriptionsI2C Mode Register Icmdr I2C Mode Register Icmdr Field DescriptionsRM bit is dont care Icmdr Bit Bus Activity DescriptionHow the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX BitIntcode 10 I2C Interrupt Vector Register IcivrI2C Interrupt Vector Register Icivr Field Descriptions Ignack BCM R/W-0 R/W-1 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions IgnackIpsc 12 I2C Prescaler Register IcpscI2C Prescaler Register Icpsc Field Descriptions Type 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 I2CDocument Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP TI E2E Community Home
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