Texas Instruments TMS320C642X manual I2C Data Transmit Register Icdxr

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Registers

3.8I2C Data Transmit Register (ICDXR)

The CPU or EDMA writes transmit data to the I2C data transmit register (ICDXR). The ICDXR can accept a data value of up to 8 bits. When writing a data value with fewer than 8 bits, the written data must be right-aligned in the D bits. The number of data bits is selected by the bit count bits (BC) of ICMDR. Once data is written to ICDXR, the I2C copies the contents of ICDXR into the I2C transmit shift register (ICXSR). The ICXSR shifts out the transmit data from the SDA pin. The CPU and the EDMA controller cannot access ICXSR.

The I2C data transmit register (ICDXR) is shown in Figure 21 and described in Table 13.

Figure 21. I2C Data Transmit Register (ICDXR)

31				16
	Reserved

		R-0
15	8	7		0

	Reserved			D

	R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 13. I2C Data Transmit Register (ICDXR) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	These reserved bit locations are always read as zeros. A value written to this field has no effect.

7-0	D	0-FFh	Transmit data.

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	31
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralClock Synchronization Signal DescriptionsInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data FormatsACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data FormatOperating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating ModesI2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit GenerationArbitration Arbitration Procedure Between Two Master-TransmittersInitialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions OaddrAAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy NackSdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull XsmtAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register IcclkhI2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitI2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-1I2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 TypeReference Additions/Modifications/Deletions Document Revision HistoryTI E2E Community Home Products ApplicationsDSP Rfid