Texas Instruments TMS320C642X manual Purpose of the Peripheral, Features Not Supported

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User's Guide

SPRUEN0D – March 2011

Inter-Integrated Circuit (I2C) Peripheral

1Introduction

This document describes the operation of the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The scope of this document assumes that you are familiar with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1.

1.1Purpose of the Peripheral

The I2C peripheral provides an interface between the TMS320C642x DSP and other devices that are compliant with the I2C-bus specification and connected by way of an I2C-bus. External components that are attached to this two-wire serial bus can transmit and receive data that is up to eight bits wide both to and from the DSP through the I2C peripheral.

1.2Features

The I2C peripheral has the following features:

•Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):

–Support for byte format transfer

–7-bit and 10-bit addressing modes

–General call

–START byte mode

–Support for multiple master-transmitters and slave-receivers mode

–Support for multiple slave-transmitters and master-receivers mode

–Combined master transmit/receive and receive/transmit mode

–I2C data transfer rate of from 10 kbps up to 400 kbps (Philips I2C rate)

•2 to 8 bit format transfer

•Free data format mode

•One read DMA event and one write DMA event that the DMA can use

•Seven interrupts that the CPU can use

•Peripheral enable/disable capability

1.2.1Features Not Supported

•High-speed mode

•CBUS-compatibility mode

•The combined format in 10-bit addressing mode (the I2C sends the slave address the second byte every time it sends the slave address the first byte).

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	7
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralClock Synchronization Signal DescriptionsInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data FormatsACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data FormatOperating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating ModesI2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit GenerationArbitration Arbitration Procedure Between Two Master-TransmittersInitialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions OaddrAAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy NackSdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull XsmtAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register IcclkhI2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitI2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-1I2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 TypeReference Additions/Modifications/Deletions Document Revision HistoryTI E2E Community Home Products ApplicationsDSP Rfid