Texas Instruments TMS320C642X manual An acknowledge bit ACK has been sent by the receiver

Page 27

www.ti.comRegisters

Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued)

Bit

Field

Value

Description

 

 

 

 

1

NACK

 

No-acknowledgment interrupt flag bit. NACK applies when the I2C is a transmitter (master or slave).

 

 

 

NACK indicates whether the I2C has detected an acknowledge bit (ACK) or a no-acknowledge bit

 

 

 

(NACK) from the receiver. The CPU can poll NACK or use the NACK interrupt request.

 

 

0

ACK received/NACK is not received. NACK is cleared by one of the following events:

 

 

 

• An acknowledge bit (ACK) has been sent by the receiver.

 

 

 

• NACK is manually cleared. To clear this bit, write a 1 to it.

 

 

 

• The CPU reads the interrupt vector register (ICIVR) when the register contains the code for a NACK

 

 

 

interrupt.

 

 

 

• The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset).

 

 

1

NACK bit is received. The hardware detects that a no-acknowledge (NACK) bit has been received.

 

 

 

Note: While the I2C performs a general call transfer, NACK is 1, even if one or more slaves send

 

 

 

acknowledgment.

 

 

 

 

0

AL

 

Arbitration-lost interrupt flag bit (only applicable when the I2C is a master-transmitter). AL primarily

 

 

 

indicates when the I2C has lost an arbitration contest with another master-transmitter. The CPU can poll

 

 

 

AL or use the AL interrupt request.

 

 

0

Arbitration is not lost. AL is cleared by one of the following events:

 

 

 

• AL is manually cleared. To clear this bit, write a 1 to it.

 

 

 

• The CPU reads the interrupt vector register (ICIVR) when the register contains the code for an AL

 

 

 

interrupt.

 

 

 

• The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset).

 

 

1

Arbitration is lost. AL is set by one of the following events:

 

 

 

• The I2C senses that it has lost an arbitration with two or more competing transmitters that started a

 

 

 

transmission almost simultaneously.

 

 

 

• The I2C attempts to start a transfer while the BB (bus busy) bit is set to 1.

 

 

 

When AL is set to 1, the MST and STP bits of ICMDR are cleared, and the I2C becomes a

 

 

 

slave-receiver.

 

 

 

 

SPRUEN0D –March 2011

Inter-Integrated Circuit (I2C) Peripheral

27

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© 2011, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralSignal Descriptions Clock SynchronizationInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data FormatsACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data FormatOperating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating ModesI2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit GenerationArbitration Arbitration Procedure Between Two Master-TransmittersInitialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions OaddrAAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy NackSdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull XsmtAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register IcclkhI2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX Bit10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-112 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 TypeReference Additions/Modifications/Deletions Document Revision HistoryTI E2E Community Home Products ApplicationsDSP Rfid
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