Texas Instruments TMS320C642X manual Configuring the I2C in Slave Receiver and Transmitter Mode

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Peripheral Architecture

2.12.1Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPU

The following initialization procedure is for the I2C controller configured in Master Receiver mode. The CPU is used to move data from the I2C receive register to CPU memory (memory accessible by the CPU).

1.Enable I2C clock from the Power and Sleep Controller (see the TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (SPRUEN8)).

2.Place I2C in reset (clear IRS = 0 in ICMDR).

3.Configure ICMDR:

•Configure I2C as Master (MST = 1).

•Indicate the I2C configuration to be used; for example, Data Receiver (TRX = 0)

•Indicate 7-bit addressing is to be used (XA = 0).

•Disable repeat mode (RM = 0).

•Disable loopback mode (DLB = 0).

•Disable free data format (FDF = 0).

•Optional: Disable start byte mode if addressing a fully fledged I2C device (STB = 0).

•Set number of bits to transfer to be 8 bits (BC = 0).

4.Configure Slave Address: the I2C device this I2C master would be addressing (ICSAR = 7BIT ADDRESS).

5.Configure the peripheral clock operation frequency (ICPSC). This value should be selected in such a way that the frequency is between 6.7 and 13.3 MHz.

6.Configure I2C master clock frequency:

•Configure the low-time divider value (ICCLKL).

•Configure the high-time divider value (ICCLKH).

7.Make sure the interrupt status register (ICSTR) is cleared:

•Read ICSTR and write it back (write 1 to clear) ICSTR = ICSTR

•Read ICIVR until it is 0.

8.Take I2C controller out of reset: enable I2C controller (set IRS bit = 1 in ICMDR).

9.Wait until bus busy bit is cleared (BB = 0 in ICSTR).

10.Generate a START event, followed by Slave Address, etc. (set STT = 1 in ICMDR).

11.Wait until data is received (ICRRDY = 1 in ICSTR).

12.Read data:

•If ICRRDY = 1 in ICSTR, then read ICDRR.

•Perform the previous two steps until receiving one byte short of the entire byte expecting to receive.

13.Configure the I2C controller not to generate an ACK on the next/final byte reception: set NACKMOD bit for the I2C to generate a NACK on the last byte received (set NACKMOD = 1 in ICMDR).

14.End transfer/release bus when transfer is done. Generate a STOP event (set STP = 1 in ICMDR).

2.12.2Configuring the I2C in Slave Receiver and Transmitter Mode

The following initialization procedure is for the I2C controller configured in Slave Receiver and Transmitter mode.

1.Enable I2C clock from PSC Level. Do this so that you will be able to configure the I2C registers.

2.Place I2C in reset (clear IRS = 0 in ICMDR).

3.Assign the Address (a 7 bit or 10 bit address) that the I2C Controller will be responding to. This is the Address that the Master is going to broadcast when attempting to start communication with this slave device; I2C Controller.

•If the I2C is able to respond to 7-bit Addressing: Configure XA = 0

•If the I2C is able to respond to 10-bit Addressing: Configure XA = 1

•Program ICOAR = Assigned Address (7-bit or 10-bit Address)

SPRUEN0D –March 2011

Inter-Integrated Circuit (I2C) Peripheral

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralClock Synchronization Signal DescriptionsInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data FormatsACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data FormatOperating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating ModesI2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit GenerationArbitration Arbitration Procedure Between Two Master-TransmittersInitialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions OaddrAAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy NackSdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull XsmtAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register IcclkhI2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitI2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-1I2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 TypeReference Additions/Modifications/Deletions Document Revision HistoryTI E2E Community Home Products ApplicationsDSP Rfid
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