Texas Instruments TMS320C642X manual How the MST and FDF Bits Affect the Role of TRX Bit

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Table 16. How the MST and FDF Bits Affect the Role of TRX Bit

ICMDR Bit
MST	FDF	I2C State	Function of TRX Bit

0	0	In slave mode but not free data format	TRX is a don't care. Depending on the command from the master, the I2C
		mode	responds as a receiver or a transmitter.
0	1	In slave mode and free data format	The free data format mode requires that the transmitter and receiver be
		mode	fixed. TRX identifies the role of the I2C:

TRX = 0: The I2C is a receiver.

TRX = 1: The I2C is a transmitter.

10 In master mode but not free data format mode

TRX identifies the role of the I2C:

TRX = 0: The I2C is a receiver.

TRX = 1: The I2C is a transmitter.

1	1	In master mode and free data format	The free data format mode requires that the transmitter and receiver be
		mode	fixed. TRX identifies the role of the I2C:

TRX = 0: The I2C is a receiver.

TRX = 1: The I2C is a transmitter.

Figure 23. Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit

	I2C peripheral
			DLB
To internal I2C logic	SCL_IN		0	SCL
	SCL_IN

			1	0
From internal I2C logic	SCL_OUT
From internal I2C logic
			DLB
To internal I2C logic
To ARM CPU or EDMA			0	SDA
To ARM CPU or EDMA	ICDRR		ICRSR
		DLB	1	0
		DLB
From ARM CPU or EDMA	ICSAR	0
	ICSAR	0
From ARM CPU or EDMA	ICOAR	1	ICXSR
	ICOAR	1	ICXSR
From ARM CPU or EDMA	ICDXR
	ICDXR
			Address/data

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	35
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFeatures Not Supported Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralInput and Output Voltage Levels Signal DescriptionsClock Synchronization Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data FormatsACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data FormatOperating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating ModesI2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit GenerationArbitration Arbitration Procedure Between Two Master-TransmittersInitialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture DMA Events Generated by the I2C Peripheral Power ManagementInterrupt Support Acronym Register Description Emulation ConsiderationsInter-Integrated Circuit I2C Registers Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions OaddrAAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy NackSdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull XsmtAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register IcclkhIcdc I2C Data Count Register IccntI2C Data Count Register Iccnt Field Descriptions I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitIntcode 10 I2C Interrupt Vector Register IcivrI2C Interrupt Vector Register Icivr Field Descriptions Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-1Ipsc 12 I2C Prescaler Register IcpscI2C Prescaler Register Icpsc Field Descriptions I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 TypeReference Additions/Modifications/Deletions Document Revision HistoryTI E2E Community Home Products ApplicationsDSP Rfid