Texas Instruments TMS320C642X manual Read This First

Page 6

Preface

SPRUEN0D – March 2011

Read This First

About This Manual

This document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices that are compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. The scope of this document assumes that you are familiar with the I2C-bus specification.

Notational Conventions

This document uses the following conventions.

•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

•Registers in this document are shown in figures and described in tables.

–Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

–Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320C642x Digital Signal Processor (DSP). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the C642x DSP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUEM3 — TMS320C642x DSP Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the TMS320C642x Digital Signal Processor (DSP).

SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

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Preface

SPRUEN0D –March 2011

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementBus Structure Multiple I2C Modules ConnectedClocking Diagram for the I2C Peripheral Clock GenerationSignal Descriptions Clock SynchronizationInput and Output Voltage Levels Start and Stop Conditions Data ValiditySerial Data Formats 1 7-Bit Addressing FormatFree Data Format Using a Repeated Start Condition2 10-Bit Addressing Format ACKOperating Modes Operating Mode DescriptionEndianness Considerations Operating Modes of the I2C PeripheralNack Bit Generation Nack Bit GenerationWays to Generate a Nack Bit I2C Peripheral Condition Basic OptionalArbitration Procedure Between Two Master-Transmitters ArbitrationHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description Oaddr I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions Bit Field Value DescriptionSCD Icxrdy Icrrdy Ardy Nack I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions AASSdir Nacksnt Rsfull Xsmt I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions SdirBit Field AD0An acknowledge bit ACK has been sent by the receiver 2 I2C Clock High-Time Divider Register Icclkh I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl IcclI2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Data Receive Register Icdrr Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field DescriptionsI2C Mode Register Icmdr I2C Mode Register Icmdr Field DescriptionsRM bit is dont care Icmdr Bit Bus Activity DescriptionHow the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX Bit10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode Ignack BCM R/W-0 R/W-1 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack12 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc Type 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 I2CDocument Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP TI E2E Community Home
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