Texas Instruments TMS320C642X Functional Block Diagram, Industry Standards Compliance Statement

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Introduction

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1.3Functional Block Diagram

A block diagram of the I2C peripheral is shown in Figure 1. Refer to Section 2 for detailed information about the architecture of the I2C peripheral.

Figure 1. I2C Peripheral Block Diagram

	I2C peripheral		Peripheral data bus
	ICXSR	ICDXR
SDA			CPU
	ICRSR	ICDRR
		Control/status	EDMA
SCL	Clock	registers
SCL	synchronizer
	synchronizer
	Prescaler
	Noise filters	I2C INT	Interrupt
		I2C INT	to CPU
			to CPU
	Arbitrator	ICREVT	Sync events to
		ICXEVT	EDMA controller

1.4Industry Standard(s) Compliance Statement

The I2C peripheral is compliant with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1.

Inter-Integrated Circuit (I2C) Peripheral

SPRUEN0D –March 2011

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFeatures Not Supported Functional Block Diagram Industry Standards Compliance StatementBus Structure Multiple I2C Modules ConnectedClocking Diagram for the I2C Peripheral Clock GenerationInput and Output Voltage Levels Signal DescriptionsClock Synchronization Start and Stop Conditions Data ValiditySerial Data Formats 1 7-Bit Addressing FormatUsing a Repeated Start Condition 2 10-Bit Addressing FormatFree Data Format ACKOperating Mode Description Endianness ConsiderationsOperating Modes Operating Modes of the I2C PeripheralNack Bit Generation Ways to Generate a Nack BitNack Bit Generation I2C Peripheral Condition Basic OptionalArbitration Procedure Between Two Master-Transmitters ArbitrationReset Considerations Software Reset ConsiderationsHardware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture DMA Events Generated by the I2C Peripheral Power ManagementInterrupt Support Acronym Register Description Emulation ConsiderationsInter-Integrated Circuit I2C Registers I2C Own Address Register Icoar I2C Own Address Register Icoar Field DescriptionsOaddr Bit Field Value DescriptionI2C Interrupt Mask Register Icimr I2C Interrupt Mask Register Icimr Field DescriptionsSCD Icxrdy Icrrdy Ardy Nack AASI2C Interrupt Status Register Icstr I2C Interrupt Status Register Icstr Field DescriptionsSdir Nacksnt Rsfull Xsmt SdirBit Field AD0An acknowledge bit ACK has been sent by the receiver I2C Clock Divider Registers Icclkl and Icclkh 1 I2C Clock Low-Time Divider Register Icclkl2 I2C Clock High-Time Divider Register Icclkh IcclIcdc I2C Data Count Register IccntI2C Data Count Register Iccnt Field Descriptions I2C Data Receive Register Icdrr I2C Slave Address Register IcsarI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field DescriptionsI2C Mode Register Icmdr I2C Mode Register Icmdr Field DescriptionsRM bit is dont care Icmdr Bit Bus Activity DescriptionHow the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX BitIntcode 10 I2C Interrupt Vector Register IcivrI2C Interrupt Vector Register Icivr Field Descriptions 11 I2C Extended Mode Register Icemdr I2C Extended Mode Register Icemdr Field DescriptionsIgnack BCM R/W-0 R/W-1 IgnackIpsc 12 I2C Prescaler Register IcpscI2C Prescaler Register Icpsc Field Descriptions 13 I2C Peripheral Identification Register ICPID1 14 I2C Peripheral Identification Register ICPID2Type I2CDocument Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid TI E2E Community Home