Texas Instruments TMS320C642X I2C Data Receive Register Icdrr, I2C Slave Address Register Icsar

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Registers

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3.6I2C Data Receive Register (ICDRR)

The I2C data receive register (ICDRR) is used to read the receive data. The ICDRR can receive a data value of up to 8 bits; data values with fewer than 8 bits are right-aligned in the D bits and the remaining D bits are undefined. The number of data bits is selected by the bit count bits (BC) of ICMDR. The I2C receive shift register (ICRSR) shifts in the received data from the SDA pin. Once data is complete, the I2C copies the contents of ICRSR into ICDRR. The CPU and the EDMA controller cannot access ICRSR.

The I2C data receive register (ICDRR) is shown in Figure 19 and described in Table 11.

Figure 19. I2C Data Receive Register (ICDRR)

31

 

 

 

16

 

Reserved

 

 

 

R-0

 

15

8

7

0

 

 

 

 

 

 

Reserved

 

 

D

 

R-0

 

 

R-0

LEGEND: R = Read only; -n= value after reset

Table 11. I2C Data Receive Register (ICDRR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-8

Reserved

0

These reserved bit locations are always read as zeros. A value written to this field has no effect.

 

 

 

 

7-0

D

0-FFh

Receive data.

 

 

 

 

3.7I2C Slave Address Register (ICSAR)

The I2C slave address register (ICSAR) contains a 7-bit or 10-bit slave address. When the I2C is not using the free data format (FDF = 0 in ICMDR), it uses this address to initiate data transfers with a slave or slaves. When the address is nonzero, the address is for a particular slave. When the address is 0, the address is a general call to all slaves. If the 7-bit addressing mode is selected (XA = 0 in ICMDR), only bits 6-0 of ICSAR are used; bits 9-7 are ignored. The I2C slave address register (ICSAR) is shown in Figure 20 and described in Table 12.

Figure 20. I2C Slave Address Register (ICSAR)

31

 

 

16

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

15

10

9

0

 

 

 

 

 

Reserved

 

SADDR

 

 

 

 

 

R-0

 

R/W-3FFh

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 12. I2C Slave Address Register (ICSAR) Field Descriptions

Bit

 

Field

Value

Description

 

 

 

 

 

 

31-10

 

Reserved

0

These reserved bit locations are always read as zeros. A value written to this field has no effect.

 

 

 

 

 

 

9-0

 

SADDR

0-3FFh

Slave address. Provides the slave address of the I2C.

 

 

 

 

 

In 7-bit addressing mode (XA = 0 in ICMDR): bits 6-0 provide the 7-bit slave address that the I2C

 

 

 

 

transmits when it is in the master-transmitter mode. Bits 9-7 are ignored.

 

 

 

 

In 10-bit addressing mode (XA = 1 in ICMDR): Bits 9-0 provide the 10-bit slave address that the

 

 

 

 

I2C transmits when it is in the master-transmitter mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

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Inter-Integrated Circuit (I2C) Peripheral

SPRUEN0D –March 2011

 

 

 

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementBus Structure Multiple I2C Modules ConnectedClocking Diagram for the I2C Peripheral Clock GenerationSignal Descriptions Clock SynchronizationInput and Output Voltage Levels Start and Stop Conditions Data ValiditySerial Data Formats 1 7-Bit Addressing FormatFree Data Format Using a Repeated Start Condition2 10-Bit Addressing Format ACKOperating Modes Operating Mode DescriptionEndianness Considerations Operating Modes of the I2C PeripheralNack Bit Generation Nack Bit GenerationWays to Generate a Nack Bit I2C Peripheral Condition Basic OptionalArbitration Procedure Between Two Master-Transmitters ArbitrationHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description Oaddr I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions Bit Field Value DescriptionSCD Icxrdy Icrrdy Ardy Nack I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions AASSdir Nacksnt Rsfull Xsmt I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions SdirBit Field AD0An acknowledge bit ACK has been sent by the receiver 2 I2C Clock High-Time Divider Register Icclkh I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl IcclI2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Data Receive Register Icdrr Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field DescriptionsI2C Mode Register Icmdr I2C Mode Register Icmdr Field DescriptionsRM bit is dont care Icmdr Bit Bus Activity DescriptionHow the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX Bit10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode Ignack BCM R/W-0 R/W-1 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack12 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc Type 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 I2CDocument Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP TI E2E Community Home
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