Texas Instruments TMS320C642X I2C Own Address Register Icoar, Oaddr, Bit Field Value Description

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Registers

3.1I2C Own Address Register (ICOAR)

The I2C own address register (ICOAR) is used to specify its own slave address, which distinguishes it from other slaves connected to the I2C-bus. If the 7-bit addressing mode is selected (XA = 0 in ICMDR), only bits 6-0 are used; bits 9-7 are ignored.

The I2C own address register (ICOAR) is shown in Figure 13 and described in Table 5.

Figure 13. I2C Own Address Register (ICOAR)

31			16
			Reserved

			R-0
15	10	9	0

	Reserved		OADDR

	R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 5. I2C Own Address Register (ICOAR) Field Descriptions

Bit	Field	Value	Description

31-10	Reserved	0	These reserved bit locations are always read as zeros. A value written to this field has no effect.

9-0	OADDR	0-3FFh	Own slave address. Provides the slave address of the I2C.
			In 7-bit addressing mode (XA = 0 in ICMDR): bits 6-0 provide the 7-bit slave address of the I2C. Bits 9-7
			are ignored.
			In 10-bit addressing mode (XA = 1 in ICMDR): bits 9-0 provide the 10-bit slave address of the I2C.

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	23
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFeatures Not Supported Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralInput and Output Voltage Levels Signal DescriptionsClock Synchronization Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data FormatsACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data FormatOperating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating ModesI2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit GenerationArbitration Arbitration Procedure Between Two Master-TransmittersInitialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture DMA Events Generated by the I2C Peripheral Power ManagementInterrupt Support Acronym Register Description Emulation ConsiderationsInter-Integrated Circuit I2C Registers Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions OaddrAAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy NackSdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull XsmtAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register IcclkhIcdc I2C Data Count Register IccntI2C Data Count Register Iccnt Field Descriptions I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitIntcode 10 I2C Interrupt Vector Register IcivrI2C Interrupt Vector Register Icivr Field Descriptions Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-1Ipsc 12 I2C Prescaler Register IcpscI2C Prescaler Register Icpsc Field Descriptions I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 TypeReference Additions/Modifications/Deletions Document Revision HistoryTI E2E Community Home Products ApplicationsDSP Rfid