Texas Instruments TMS320C642X manual Arbitration Procedure Between Two Master-Transmitters

Page 17

www.ti.com

Peripheral Architecture

2.10 Arbitration

If two or more master-transmitters simultaneously start a transmission on the same bus, an arbitration procedure is invoked. The arbitration procedure uses the data presented on the serial data bus (SDA) by the competing transmitters. Figure 12 illustrates the arbitration procedure between two devices. The first master-transmitter, which drives SDA high, is overruled by another master-transmitter that drives SDA low. The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value. Should two or more devices send identical first bytes, arbitration continues on the subsequent bytes.

If the I2C peripheral is the losing master, it switches to the slave-receiver mode, sets the arbitration lost (AL) flag, and generates the arbitration-lost interrupt.

If during a serial transfer the arbitration procedure is still in progress when a repeated START condition or a STOP condition is transmitted to SDA, the master-transmitters involved must send the repeated START condition or the STOP condition at the same position in the format frame. Arbitration is not allowed between:

A repeated START condition and a data bit

A STOP condition and a data bit

A repeated START condition and a STOP condition

Figure 12. Arbitration Procedure Between Two Master-Transmitters

Bus line

 

 

 

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

Device #1 lost arbitration

 

 

 

 

 

and switches off

 

 

Data from

1

0

 

 

 

 

device #1

 

 

 

 

 

 

 

 

 

 

Data from

1

0

0

1

0

1

device #2

 

 

 

 

 

 

Bus line

1

0

0

1

0

1

SDA

 

 

 

 

 

 

SPRUEN0D –March 2011

Inter-Integrated Circuit (I2C) Peripheral

17

Submit Documentation Feedback

 

 

© 2011, Texas Instruments Incorporated

Image 17
Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFeatures Not Supported Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralInput and Output Voltage Levels Signal DescriptionsClock Synchronization Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data Formats2 10-Bit Addressing Format Using a Repeated Start ConditionFree Data Format ACKEndianness Considerations Operating Mode DescriptionOperating Modes Operating Modes of the I2C PeripheralWays to Generate a Nack Bit Nack Bit GenerationNack Bit Generation I2C Peripheral Condition Basic OptionalArbitration Arbitration Procedure Between Two Master-TransmittersSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture DMA Events Generated by the I2C Peripheral Power ManagementInterrupt Support Acronym Register Description Emulation ConsiderationsInter-Integrated Circuit I2C Registers I2C Own Address Register Icoar Field Descriptions I2C Own Address Register IcoarOaddr Bit Field Value DescriptionI2C Interrupt Mask Register Icimr Field Descriptions I2C Interrupt Mask Register IcimrSCD Icxrdy Icrrdy Ardy Nack AASI2C Interrupt Status Register Icstr Field Descriptions I2C Interrupt Status Register IcstrSdir Nacksnt Rsfull Xsmt SdirAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver 1 I2C Clock Low-Time Divider Register Icclkl I2C Clock Divider Registers Icclkl and Icclkh2 I2C Clock High-Time Divider Register Icclkh IcclIcdc I2C Data Count Register IccntI2C Data Count Register Iccnt Field Descriptions I2C Slave Address Register Icsar I2C Data Receive Register IcdrrI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitIntcode 10 I2C Interrupt Vector Register IcivrI2C Interrupt Vector Register Icivr Field Descriptions I2C Extended Mode Register Icemdr Field Descriptions 11 I2C Extended Mode Register IcemdrIgnack BCM R/W-0 R/W-1 IgnackIpsc 12 I2C Prescaler Register IcpscI2C Prescaler Register Icpsc Field Descriptions 14 I2C Peripheral Identification Register ICPID2 13 I2C Peripheral Identification Register ICPID1Type I2CReference Additions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid TI E2E Community Home