Texas Instruments TMS320C642X Emulation Considerations, Inter-Integrated Circuit I2C Registers

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Registers

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2.16 Emulation Considerations

The response of the I2C events to emulation suspend events (such as halts and breakpoints) is controlled by the FREE bit in the I2C mode register (ICMDR). The I2C peripheral either stops exchanging data (FREE = 0) or continues to run (FREE = 1) when an emulation suspend event occurs. How the I2C peripheral terminates data transactions is affected by whether the I2C peripheral is acting as a master or a slave. For more information, see the description of the FREE bit in ICMDR (see Section 3.9).

3Registers

Table 4 lists the memory-mapped registers for the inter-integrated circuit (I2C) peripheral. See the device-specific data manual for the memory address of these registers. All other register offset addresses not listed in Table 4 should be considered as reserved locations and the register contents should not be modified.

Table 4. Inter-Integrated Circuit (I2C) Registers

Offset	Acronym	Register Description	Section
0h	ICOAR	I2C Own Address Register	Section 3.1
4h	ICIMR	I2C Interrupt Mask Register	Section 3.2
8h	ICSTR	I2C Interrupt Status Register	Section 3.3
Ch	ICCLKL	I2C Clock Low-Time Divider Register	Section 3.4
10h	ICCLKH	I2C Clock High-Time Divider Register	Section 3.4
14h	ICCNT	I2C Data Count Register	Section 3.5
18h	ICDRR	I2C Data Receive Register	Section 3.6
1Ch	ICSAR	I2C Slave Address Register	Section 3.7
20h	ICDXR	I2C Data Transmit Register	Section 3.8
24h	ICMDR	I2C Mode Register	Section 3.9
28h	ICIVR	I2C Interrupt Vector Register	Section 3.10
2Ch	ICEMDR	I2C Extended Mode Register	Section 3.11
30h	ICPSC	I2C Prescaler Register	Section 3.12
34h	ICPID1	I2C Peripheral Identification Register 1	Section 3.13
38h	ICPID2	I2C Peripheral Identification Register 2	Section 3.13

22	Inter-Integrated Circuit (I2C) Peripheral	SPRUEN0D –March 2011
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementBus Structure Multiple I2C Modules ConnectedClocking Diagram for the I2C Peripheral Clock GenerationClock Synchronization Signal DescriptionsInput and Output Voltage Levels Start and Stop Conditions Data ValiditySerial Data Formats 1 7-Bit Addressing FormatFree Data Format Using a Repeated Start Condition2 10-Bit Addressing Format ACKOperating Modes Operating Mode DescriptionEndianness Considerations Operating Modes of the I2C PeripheralNack Bit Generation Nack Bit GenerationWays to Generate a Nack Bit I2C Peripheral Condition Basic OptionalArbitration Procedure Between Two Master-Transmitters ArbitrationHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description Oaddr I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions Bit Field Value DescriptionSCD Icxrdy Icrrdy Ardy Nack I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions AASSdir Nacksnt Rsfull Xsmt I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions SdirBit Field AD0An acknowledge bit ACK has been sent by the receiver 2 I2C Clock High-Time Divider Register Icclkh I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl IcclI2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Data Receive Register Icdrr Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field DescriptionsI2C Mode Register Icmdr I2C Mode Register Icmdr Field DescriptionsRM bit is dont care Icmdr Bit Bus Activity DescriptionHow the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX BitI2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode Ignack BCM R/W-0 R/W-1 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions IgnackI2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc Type 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 I2CDocument Revision History Reference Additions/Modifications/DeletionsRfid Products ApplicationsDSP TI E2E Community Home