Texas Instruments TMS320C642X manual Bus Structure, Multiple I2C Modules Connected

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Peripheral Architecture

2Peripheral Architecture

The I2C peripheral consists of the following primary blocks:

•A serial interface: one data pin (SDA) and one clock pin (SCL)

•Data registers to temporarily hold receive data and transmit data traveling between the SDA pin and the CPU or the EDMA controller

•Control and status registers

•A peripheral data bus interface to enable the CPU and the EDMA controller to access the I2C peripheral registers

•A clock synchronizer to synchronize the I2C input clock (from the processor clock generator) and the clock on the SCL pin, and to synchronize data transfers with masters of different clock speeds

•A prescaler to divide down the input clock that is driven to the I2C peripheral

•A noise filter on each of the two pins, SDA and SCL

•An arbitrator to handle arbitration between the I2C peripheral (when it is a master) and another master

•Interrupt generation logic, so that an interrupt can be sent to the CPU

•EDMA event generation logic, so that activity in the EDMA controller can be synchronized to data reception and data transmission in the I2C peripheral

Figure 1 shows the four registers used for transmission and reception. The CPU or the EDMA controller writes data for transmission to ICDXR and reads received data from ICDRR. When the I2C peripheral is configured as a transmitter, data written to ICDXR is copied to ICXSR and shifted out on the SDA pin one bit a time. When the I2C peripheral is configured as a receiver, received data is shifted into ICRSR and then copied to ICDRR.

2.1Bus Structure

Figure 1 shows how the I2C peripheral is connected to the I2C bus. The I2C bus is a multi-master bus that supports a multi-master mode. This allows more than one device capable of controlling the bus that is connected to it. A unique address recognizes each I2C device. Each I2C device can operate as either transmitter or receiver, depending on the function of the device. Devices that are connected to the I2C bus can be considered a master or slave when performing data transfers, in addition to being a transmitter or receiver.

NOTE: A master device is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device that is addressed by this master is considered a slave during this transfer.

An example of multiple I2C modules that are connected for a two-way transfer from one device to other devices is shown in Figure 2.

Figure 2. Multiple I2C Modules Connected

VDD

Pull-up resistors

Serial data (SDA) Serial clock (SCL)

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I2C

 

I2C

 

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I2C

 

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EPROM

 

I2C

 

 

 

SPRUEN0D –March 2011

Inter-Integrated Circuit (I2C) Peripheral

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© 2011, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralSignal Descriptions Clock SynchronizationInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data Formats2 10-Bit Addressing Format Using a Repeated Start ConditionFree Data Format ACKEndianness Considerations Operating Mode DescriptionOperating Modes Operating Modes of the I2C PeripheralWays to Generate a Nack Bit Nack Bit GenerationNack Bit Generation I2C Peripheral Condition Basic OptionalArbitration Arbitration Procedure Between Two Master-TransmittersSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description I2C Own Address Register Icoar Field Descriptions I2C Own Address Register IcoarOaddr Bit Field Value DescriptionI2C Interrupt Mask Register Icimr Field Descriptions I2C Interrupt Mask Register IcimrSCD Icxrdy Icrrdy Ardy Nack AASI2C Interrupt Status Register Icstr Field Descriptions I2C Interrupt Status Register IcstrSdir Nacksnt Rsfull Xsmt SdirAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver 1 I2C Clock Low-Time Divider Register Icclkl I2C Clock Divider Registers Icclkl and Icclkh2 I2C Clock High-Time Divider Register Icclkh IcclI2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Slave Address Register Icsar I2C Data Receive Register IcdrrI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX Bit10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode I2C Extended Mode Register Icemdr Field Descriptions 11 I2C Extended Mode Register IcemdrIgnack BCM R/W-0 R/W-1 Ignack12 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc 14 I2C Peripheral Identification Register ICPID2 13 I2C Peripheral Identification Register ICPID1Type I2CReference Additions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid TI E2E Community Home
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