Texas Instruments TMS320C642X 11 I2C Extended Mode Register Icemdr, Ignack BCM R/W-0 R/W-1, Bcm

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Registers

3.11 I2C Extended Mode Register (ICEMDR)

The I2C extended mode register (ICEMDR) is used to indicate which condition generates a transmit data ready interrupt.

The I2C extended mode register (ICEMDR) is shown in Figure 25 and described in Table 18.

Figure 25. I2C Extended Mode Register (ICEMDR)

31

Reserved

R-0

15

Reserved

R-0

LEGEND: R/W = Read/Write; R= Read only; -n= value after reset

16

10

IGNACK BCM R/W-0 R/W-1

Table 18. I2C Extended Mode Register (ICEMDR) Field Descriptions

Bit	Field	Value	Description

31-2	Reserved	0	These reserved bit locations are always read as zeros. A value written to this field has no effect.

1	IGNACK		Ignore NACK mode.
		0	Master transmitter operates normally, that is, it discontinues the data transfer and sets the ARDY and
			NACK bits in ICSTR when receiving a NACK from the slave.
		1	Master transmitter ignores a NACK from the slave.

0	BCM		Backward compatibility mode bit. Determines which condition generates a transmit data ready interrupt.
			The BCM bit only has an effect when the I2C is operating as a slave-transmitter.
		0	The transmit data ready interrupt is generated when the master requests more data by sending an
			acknowledge signal after the transmission of the last data.
		1	The transmit data ready interrupt is generated when the data in ICDXR is copied to ICXSR.

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	37
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralClock Synchronization Signal DescriptionsInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data Formats2 10-Bit Addressing Format Using a Repeated Start ConditionFree Data Format ACKEndianness Considerations Operating Mode DescriptionOperating Modes Operating Modes of the I2C PeripheralWays to Generate a Nack Bit Nack Bit GenerationNack Bit Generation I2C Peripheral Condition Basic OptionalArbitration Arbitration Procedure Between Two Master-TransmittersSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description I2C Own Address Register Icoar Field Descriptions I2C Own Address Register IcoarOaddr Bit Field Value DescriptionI2C Interrupt Mask Register Icimr Field Descriptions I2C Interrupt Mask Register IcimrSCD Icxrdy Icrrdy Ardy Nack AASI2C Interrupt Status Register Icstr Field Descriptions I2C Interrupt Status Register IcstrSdir Nacksnt Rsfull Xsmt SdirAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver 1 I2C Clock Low-Time Divider Register Icclkl I2C Clock Divider Registers Icclkl and Icclkh2 I2C Clock High-Time Divider Register Icclkh IcclI2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Slave Address Register Icsar I2C Data Receive Register IcdrrI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitI2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode I2C Extended Mode Register Icemdr Field Descriptions 11 I2C Extended Mode Register IcemdrIgnack BCM R/W-0 R/W-1 IgnackI2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc 14 I2C Peripheral Identification Register ICPID2 13 I2C Peripheral Identification Register ICPID1Type I2CReference Additions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid TI E2E Community Home