Texas Instruments TMS320C642X manual Nack Bit Generation, Ways to Generate a Nack Bit

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2.9NACK Bit Generation

When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the acknowledge cycle on the bus. Table 2 summarizes the various ways the I2C peripheral sends a NACK bit.

	Table 2. Ways to Generate a NACK Bit
	NACK Bit Generation
I2C Peripheral
Condition	Basic	Optional
Slave-receiver mode	• Disable data transfers (STT = 0 in ICSTR).	Set the NACKMOD bit of ICMDR before the rising
		edge of the last data bit you intend to receive.
	• Allow an overrun condition (RSFULL = 1 in
	ICSTR).
	• Reset the peripheral (IRS = 0 in ICMDR)
	.
Master-receiver mode	• Generate a STOP condition (STOP = 1 in	Set the NACKMOD bit of ICMDR before the rising
AND		edge of the last data bit you intend to receive.
	ICMDR).
Repeat mode
	• Reset the peripheral (IRS = 0 in ICMDR).
(RM = 1 in ICMDR)
Master-receiver mode	• If STP = 1 in ICMDR, allow the internal data	Set the NACKMOD bit of ICMDR before the rising
AND		edge of the last data bit you intend to receive.
	counter to count down to 0 and force a STOP

Nonrepeat mode	condition.
(RM = 0 in ICMDR)
	• If STP = 0, make STP = 1 to generate a
	STOP condition.
	• Reset the peripheral (IRS = 0 in ICMDR).

16	Inter-Integrated Circuit (I2C) Peripheral	SPRUEN0D –March 2011
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