Texas Instruments TMS320C642X manual Endianness Considerations, Operating Modes

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Peripheral Architecture

2.7Endianness Considerations

When the device is configured for big-endian mode, in order for the data to be placed in the right side of the register being accessed, access to the I2C registers must be performed as follows:

•8-bit accesses: An offset of 3h must be added to the address of the register being accessed. For example, the offset address of ICDRR becomes 1Bh (18h + 3h).

•16-bit accesses: Not supported for the I2C peripheral.

•32-bit accesses: No offset is needed. For example, the offset address of ICDRR remains as 18h.

In general, software programs the CPU to use 32-bit reads and writes when accessing the I2C registers; therefore, no offset is needed. However, software usually programs the EDMA to read and write 8-bit values from the ICDDR and ICDXR registers; hence, the offset must be added.

No offset is needed to access the I2C registers when the device is configured in little-endian mode.

2.8Operating Modes

The I2C peripheral has four basic operating modes to support data transfers as a master and as a slave. See Table 1 for the names and descriptions of the modes.

If the I2C peripheral is a master, it begins as a master-transmitter and, typically, transmits an address for a particular slave. When giving data to the slave, the I2C peripheral must remain a master-transmitter. In order to receive data from a slave, the I2C peripheral must be changed to the master-receiver mode.

If the I2C peripheral is a slave, it begins as a slave-receiver and, typically, sends acknowledgment when it recognizes its slave address from a master. If the master will be sending data to the I2C peripheral, the peripheral must remain a slave-receiver. If the master has requested data from the I2C peripheral, the peripheral must be changed to the slave-transmitter mode.

 

Table 1. Operating Modes of the I2C Peripheral

 

 

Operating Mode

Description

 

 

Slave-receiver mode

The I2C peripheral is a slave and receives data from a master. All slave modules begin in this

 

mode. In this mode, serial data bits received on SDA are shifted in with the clock pulses that are

 

generated by the master. As a slave, the I2C peripheral does not generate the clock signal, but it

 

can hold SCL low while the intervention of the processor is required (RSFULL = 1 in ICSTR) after

 

data has been received.

Slave-transmitter mode

The I2C peripheral is a slave and transmits data to a master. This mode can only be entered from

 

the slave-receiver mode; the I2C peripheral must first receive a command from the master. When

 

you are using any of the 7-bit/10-bit addressing formats, the I2C peripheral enters its

 

slave-transmitter mode if the slave address is the same as its own address (in ICOAR) and the

 

 

 

= 1. As a slave-transmitter, the I2C peripheral then shifts the serial

 

master has transmitted R/W

 

data out on SDA with the clock pulses that are generated by the master. While a slave, the I2C

 

peripheral does not generate the clock signal, but it can hold SCL low while the intervention of the

 

processor is required (XSMT = 0 in ICSTR) after data has been transmitted.

Master-receiver mode

The I2C peripheral is a master and receives data from a slave. This mode can only be entered

 

from the master-transmitter mode; the I2C peripheral must first transmit a command to the slave.

 

When you are using any of the 7-bit/10-bit addressing formats, the I2C peripheral enters its

 

 

 

 

 

= 1. Serial data bits on SDA

 

master-receiver mode after transmitting the slave address and R/W

 

are shifted into the I2C peripheral with the clock pulses generated by the I2C peripheral on SCL.

 

The clock pulses are inhibited and SCL is held low when the intervention of the processor is

 

required (RSFULL = 1 in ICSTR) after data has been received.

Master-transmitter mode

The I2C peripheral is a master and transmits control information and data to a slave. All master

 

modules begin in this mode. In this mode, data assembled in any of the 7-bit/10-bit addressing

 

formats is shifted out on SDA. The bit shifting is synchronized with the clock pulses generated by

 

the I2C peripheral on SCL. The clock pulses are inhibited and SCL is held low when the

 

intervention of the processor is required (XSMT = 0 in ICSTR) after data has been transmitted.

 

 

 

 

 

 

SPRUEN0D –March 2011

Inter-Integrated Circuit (I2C) Peripheral

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© 2011, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralSignal Descriptions Clock SynchronizationInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data FormatsACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data FormatOperating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating ModesI2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit GenerationArbitration Arbitration Procedure Between Two Master-TransmittersInitialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions OaddrAAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy NackSdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull XsmtAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register IcclkhI2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX Bit10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-112 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 TypeReference Additions/Modifications/Deletions Document Revision HistoryTI E2E Community Home Products ApplicationsDSP Rfid
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