Texas Instruments TMS320C642X manual Serial Data Formats, 1 7-Bit Addressing Format

Page 13

www.ti.com

Peripheral Architecture

2.6Serial Data Formats

Figure 7 shows an example of a data transfer on the I2C-bus. The I2C peripheral supports 1-bit to 8-bit data values. Figure 7 is shown in an 8-bit data format (BC = 000 in ICMDR). Each bit put on the SDA line is equivalent to one pulse on the SCL line. The data is always transferred with the most-significant bit (MSB) first. The number of data values that can be transmitted or received is unrestricted; however, the transmitters and receivers must agree on the number of data values being transferred.

The I2C peripheral supports the following data formats:

•7-bit addressing mode

•10-bit addressing mode

•Free data format mode

Figure 7. I2C Peripheral Data Transfer

				Acknowledgement				(No-)Acknowledgement
				bit from slave				bit from receiver
SDA
	MSB
SCL
START	1	2	7	8	9	1	2	8	9	STOP
START				R/W	ACK				ACK	STOP
condition (S)				R/W	ACK				ACK	condition (P)
condition (S)										condition (P)
		Slave address						Data

2.6.17-Bit Addressing Format

In the 7-bit addressing format (Figure 8), the first byte after a START condition (S) consists of a 7-bit slave address followed by a R/W bit. The R/W bit determines the direction of the data.

•R/W = 0: The master writes (transmits) data to the addressed slave.

•R/W = 1: The master reads (receives) data from the slave.

An extra clock cycle dedicated for acknowledgment (ACK) is inserted after the R/W bit. If the slave inserts the ACK bit, n bits of data from the transmitter (master or slave, depending on the R/W bit) follow it. n is a number from 1 to 8 that the bit count (BC) bits of ICMDR determine. The receiver inserts an ACK bit after the data bits have been transferred.

Write a 0 to the expanded address enable (XA) bit of ICMDR to select the 7-bit addressing format.

Figure 8. I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)

1

7

1

1

n

1

n

1

1

S

Slave address

R/W ACK

Data

ACK

Data

ACK P

n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICM DR.

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	13
Submit Documentation Feedback

© 2011, Texas Instruments Incorporated

Image 13

Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramMultiple I2C Modules Connected Bus StructureClock Generation Clocking Diagram for the I2C PeripheralClock Synchronization Signal DescriptionsInput and Output Voltage Levels Data Validity Start and Stop Conditions1 7-Bit Addressing Format Serial Data Formats2 10-Bit Addressing Format Using a Repeated Start ConditionFree Data Format ACKEndianness Considerations Operating Mode DescriptionOperating Modes Operating Modes of the I2C PeripheralWays to Generate a Nack Bit Nack Bit GenerationNack Bit Generation I2C Peripheral Condition Basic OptionalArbitration Arbitration Procedure Between Two Master-TransmittersSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description I2C Own Address Register Icoar Field Descriptions I2C Own Address Register IcoarOaddr Bit Field Value DescriptionI2C Interrupt Mask Register Icimr Field Descriptions I2C Interrupt Mask Register IcimrSCD Icxrdy Icrrdy Ardy Nack AASI2C Interrupt Status Register Icstr Field Descriptions I2C Interrupt Status Register IcstrSdir Nacksnt Rsfull Xsmt SdirAD0 Bit FieldAn acknowledge bit ACK has been sent by the receiver 1 I2C Clock Low-Time Divider Register Icclkl I2C Clock Divider Registers Icclkl and Icclkh2 I2C Clock High-Time Divider Register Icclkh IcclI2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Slave Address Register Icsar I2C Data Receive Register IcdrrI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register IcdxrI2C Mode Register Icmdr Field Descriptions I2C Mode Register IcmdrRM bit is dont care Bus Activity Description Icmdr BitI2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX BitI2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode I2C Extended Mode Register Icemdr Field Descriptions 11 I2C Extended Mode Register IcemdrIgnack BCM R/W-0 R/W-1 IgnackI2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc 14 I2C Peripheral Identification Register ICPID2 13 I2C Peripheral Identification Register ICPID1Type I2CReference Additions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid TI E2E Community Home