Texas Instruments TMS320C642X manual Document Revision History

Page 40

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Appendix A Revision History

Table 22 lists the changes made since the previous version of this document.

Table 22. Document Revision History

Reference Additions/Modifications/Deletions

Section 1.2 Changed second bullet point.

Section 3.5 Changed first sentence in first paragraph.

Table 14 Changed Description of RM bit.

Table 17 Changed Description of INTCODE bit, value = 1h.

Changed Description of INTCODE bit, value = 7h.

40	Revision History	SPRUEN0D –March 2011
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementBus Structure Multiple I2C Modules ConnectedClocking Diagram for the I2C Peripheral Clock GenerationClock Synchronization Signal DescriptionsInput and Output Voltage Levels Start and Stop Conditions Data ValiditySerial Data Formats 1 7-Bit Addressing FormatUsing a Repeated Start Condition 2 10-Bit Addressing FormatFree Data Format ACKOperating Mode Description Endianness ConsiderationsOperating Modes Operating Modes of the I2C PeripheralNack Bit Generation Ways to Generate a Nack BitNack Bit Generation I2C Peripheral Condition Basic OptionalArbitration Procedure Between Two Master-Transmitters ArbitrationReset Considerations Software Reset ConsiderationsHardware Reset Considerations InitializationConfiguring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description I2C Own Address Register Icoar I2C Own Address Register Icoar Field DescriptionsOaddr Bit Field Value DescriptionI2C Interrupt Mask Register Icimr I2C Interrupt Mask Register Icimr Field DescriptionsSCD Icxrdy Icrrdy Ardy Nack AASI2C Interrupt Status Register Icstr I2C Interrupt Status Register Icstr Field DescriptionsSdir Nacksnt Rsfull Xsmt SdirBit Field AD0An acknowledge bit ACK has been sent by the receiver I2C Clock Divider Registers Icclkl and Icclkh 1 I2C Clock Low-Time Divider Register Icclkl2 I2C Clock High-Time Divider Register Icclkh IcclI2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Data Receive Register Icdrr I2C Slave Address Register IcsarI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field DescriptionsI2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field DescriptionsI2C Mode Register Icmdr I2C Mode Register Icmdr Field DescriptionsRM bit is dont care Icmdr Bit Bus Activity DescriptionHow the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX BitI2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode 11 I2C Extended Mode Register Icemdr I2C Extended Mode Register Icemdr Field DescriptionsIgnack BCM R/W-0 R/W-1 IgnackI2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc 13 I2C Peripheral Identification Register ICPID1 14 I2C Peripheral Identification Register ICPID2Type I2CDocument Revision History Reference Additions/Modifications/DeletionsProducts Applications DSPRfid TI E2E Community Home