Xilinx UG129 manuals
Communications > Answering Machine
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124 pages 1.6 Mb
2 Revision HistoryPreface 3 LimitationsLimited Warranty and Disclaimer Limitation of Liability Technical Support Limitations 4 Acknowledgments5 About This Guide7 Table of ContentsPreface: LimitationsLimited Warranty and Disclaimer Limitation of Liability Technical Support Limitations Preface: Acknowledgments : About This Guide Chapter 1: IntroductionPicoBlaze Microcontroller Features PicoBlaze Microcontroller Functional Blocks Why the PicoBlaze Microcontroller? Why Use a Microcontroller within an FPGA? Chapter 2: PicoBlaze Interface Signals Chapter 3: PicoBlaze Instruction SetAddress Spaces Processing Data 8 Chapter 4: InterruptsChapter 5: Scratchpad RAM Chapter 6: Input and Output Ports Chapter 7: Instruction Storage Configurations 9 Chapter 8: PerformanceChapter 9: PicoBlaze Development Tools Chapter 10: Using the PicoBlaze Microcontroller in an FPGA Design Chapter 11: Assembler Directives Chapter 12: Simulating PicoBlaze Code 10 Appendix A: Related Materials and References Appendix B: Example Program TemplatesAppendix C: PicoBlaze Instruction Set and Event Reference Appendix D: Instruction Codes Appendix E: Register and Scratchpad RAM Planning Worksheets Chapter 1 11 Introduction17 PicoBlaze Interface Signals19 PicoBlaze Instruction Set41 Interrupts45 Scratchpad RAM49 Input and Output Ports59 Instruction Storage Configurations63 PerformanceInput Clock Frequency Predicting Executing Performance Chapter 9 65 PicoBlaze Development ToolsKCPSM3 67 Mediatronix pBlazIDEConfiguring pBlazIDE for the PicoBlaze Microcontroller68 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller Chapter 9: P icoBlaze Development Tools 68 Importing KCPSM3 Code into pBlazIDEFigure 9-4: Example of How KCPSM Source Code Converts to pBlazIDE Code Figure 9-3: Converting Xilinx Syntax PicoBlaze Source Code to pBlazIDE Syntax pBlaze IDE File Edit View New Open ... Recent Files Ctrl+N Ctrl+O Export HTML Import KCMPSM Source Code Code Imported/Converted into pBlaze IDE 69 Differences Between the KCPSM3 Assembler and pBlazIDEDirectives Chapter 10 71 Using the PicoBlaze Microcontroller in an FPGA Design75 Assembler Directives81 Simulating PicoBlaze Code87 Related Materials and References89 Example Program TemplatesFigure B-1: PicoBlaze Application Program Template for KCPSM3 Assembler KCPSM3 SyntaxFigureB -1 provides a code template for creating PicoBlaze applications using the KCPSM3 assembler. Appendix : Example Program Templates 90 pBlazIDE SyntaxFigure B-2: PicoBlaze Application Program Template for KCPSM3 Assembler Appendix C 91 PicoBlaze Instruction Set and Event ReferenceADD sX, Operand Add Operand to Register sX 92 ADDCY sX, Operand Add Operand to Register sX with Carry93 AND sX, Operand Logical Bitwise AND Register sX with Operand94 CALL [Condition,] Address Call Subroutine at Specified Address, Possibly with Conditions96 COMPARE sX, Operand Compare Operand with Register sX97 DISABLE INTERRUPT Disable External Interrupt InputENABLE INTERRUPT Enable External Interrupt Input 98 FETCH sX, Operand Read Scratchpad RAM Location to Register sX99 INPUT sX, Operand Set PORT_ID to Operand, Read value on IN_PORT into Register sX100 INTERRUPT Event, When Enabled101 JUMP [Condition,] Address Jump to Specified Address, Possibly with Conditions102 LOAD sX, Operand Load Register sX with Operand103 OR sX, Operand Logical Bitwise OR Register sX with Operand104 OUTPUT sX, Operand Write Register sX Value to OUT_PORT, Set PORT_ID to Operand105 RESET Event106 RETURN [Condition] Return from Subroutine Call, Possibly with Conditions107 RETURNI [ENABLE/DISABLE] Return from Interrupt Service Routine and Enable or Disable Interrupts108 RL sX Rotate Left Register sXRR sX Rotate Right Register sX 109 SL[ 0 | 1 | X | A ] sX Shift Left Register sX110 SR[ 0 | 1 | X | A ] sX Shift Right Register sX112 STORE sX, Operand Write Register sX Value to Scratchpad RAM Location113 SUB sX, Operand Subtract Operand from Register sX114 SUBCY sX, Operand Subtract Operand from Register sX with Borrow116 TEST sX, Operand Test Bit Location in Register sX, Generate Odd Parity118 XOR sX, Operand Logical Bitwise XOR Register sX with OperandAppendix D 119 Instruction Codes123 Register and Scratchpad RAM Planning Worksheets
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