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Xilinx UG129 Instruction Storage Configurations, Standard Configuration Single 1Kx18 Block RAM

Models: UG129

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Chapter 7

Instruction Storage Configurations

The PicoBlaze™ microcontroller executes code from memory resources embedded within the FPGA. Figure 7-1shows that the PicoBlaze microcontroller actually consists of two subfunctions. The KCPSM3 module contains the PicoBlaze ALU, register file, scratchpad RAM, etc. Some form of internal memory, typically a block RAM, provides the PicoBlaze instruction store. To effective create an on-chip ROM, the block RAM’s write enable pin, WE, is held Low, disabling any potential write operations.

However, the PicoBlaze microcontroller supports other implementations that have advantages for specific applications as described below. Many of these alternate implementations leverage the extra port provided by the dual-port block RAM on Spartan®-3, Virtex®-II, and Virtex-II Pro FPGAs.

					KCPSM3
Instruction ROM				IN_PORT[7:0]	OUT_PORT[7:0]
				IN_PORT[7:0]	OUT_PORT[7:0]
				INTERRUPT	PORT_ID[7:0]
				INTERRUPT	PORT_ID[7:0]
(Block RAM)				RESET	READ_STROBE
				RESET	READ_STROBE

WE	OUT[17:0]	INSTRUCTION[17:0]	WRITE_STROBE
ADDR[9:0]		18	INTERRUPT_ACK
ADDR[9:0]			INTERRUPT_ACK
			ADDRESS[9:0]
		10	UG129_c7_01_051504
			UG129_c7_01_051504

Figure 7-1:Standard Implementation using a Single 1Kx18 Block RAM as the Instruction Store

Standard Configuration – Single 1Kx18 Block RAM

In most applications, PicoBlaze instructions are stored in a single FPGA block RAM, configured as a 1Kx18 ROM shown in Figure 7-2. The application code is assembled and ultimately compiled as part of the FPGA design. The instruction store is automatically loaded into the attached block RAM during the FPGA configuration process.

PicoBlaze 8-bit Embedded Microcontroller

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UG129 (v1.1.2) June 24, 2008

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Xilinx UG129 manual Instruction Storage Configurations, Standard Configuration Single 1Kx18 Block RAM

Contents

UG129 v1.1.2 June 24 PicoBlaze 8-bit Embedded Microcontroller User GuideVersion Revision Revision HistoryTechnical Support Limitations Limited Warranty and DisclaimerLimitations Limitation of LiabilityPreface Acknowledgments AcknowledgmentsAbout This Guide Guide ContentsPreface About This Guide Table of Contents Interrupts Performance Appendix C PicoBlaze Instruction Set and Event Reference Introduction PicoBlaze Microcontroller FeaturesIntroduction PicoBlaze Microcontroller Functional BlocksGeneral-Purpose Registers Instruction Program StoreInput/Output Arithmetic Logic Unit ALUFlags Byte Scratchpad RAMCALL/RETURN Stack ResetProgram Counter PC Program Flow ControlWhy the PicoBlaze Microcontroller? Why the PicoBlaze Microcontroller?Why Use a Microcontroller within an FPGA? Weaknesses StrengthsSignal Direction Description PicoBlaze Interface SignalsPicoBlaze Interface Signal Descriptions Readstrobe 1PicoBlaze Instruction Set alphabetical listing PicoBlaze Instruction SetEnable Interrupt Returni Disable Address Spaces Instruction 1Kx18 Direct PicoBlaze Instruction Set Processing DataLogic Instructions 3Inverting an Individual Bit Location 2Complementing a Register ValueArithmetic Instructions 616-Setting a Bit LocationSUB and Subcy Subtract Instructions 10Incrementing and Decrementing a Register Multiplication148-bit by 8-bit Multiply Routine Produces a 16-bit Product Division 168-bit by 8-bit Multiply Routine Using Hardware Multiplier18Loading a Register with Itself Acts as a NOP Instruction No Operation NOPTest and Compare Setting and Clearing Carry Flag22The Test Instruction Affects the Zero Flag Shift and Rotate Instructions 25Generate Parity for a Register Using the Test Instruction5PicoBlaze Rotate Instructions Rotate Left Rotate Right SRXProgram Flow Control Moving Data6Instruction Conditional Execution Description Program Flow ControlCALL/RETURN Program Flow Control UG129 v1.1.2 June 24 1Simple Interrupt Logic Interrupts2Example Interrupt Flow Example Interrupt FlowExample Interrupt Flow 3Interrupt Timing DiagramInterrupts Indirect Addressing Scratchpad RAMAddress Modes Direct AddressingScratchpad RAM Implementing a Look-Up TableStack Operations Stack OperationsFifo Operations Scratchpad RAM Portid Port Input and Output Ports1INPUT Operation and Fpga Interface Logic Input OperationsRegister s0 Input OperationsPORTID70 INPORT70Input and Output Ports Applications with Few Input SourcesReadstrobe Interaction with FIFOs Output Operations Output OperationsFpga Register Simple Output Structure for Few Output Destinations8Use Constant Directives to Declare Output Port Addresses 9Pipelining the Portid Decoding Improves Performance Pipelining for Maximum PerformancePipelining for Maximum Performance Effective Pipelining Improves Read Performance Repartitioning the Design for Maximum PerformanceStandard Configuration Single 1Kx18 Block RAM Instruction Storage ConfigurationsTwo PicoBlaze Microcontrollers Share a 1Kx18 Code Image Instruction Storage ConfigurationsDistributed ROM Instead of Block RAM 6Using Distributed ROM for Instruction MemoryInstruction Storage Configurations Frequency PerformanceInput Clock Frequency Predicting Executing PerformancePerformance Assembler PicoBlaze Development ToolsPicoBlaze Development Tools Assembly ErrorsInput and Output Files Mediatronix pBlazIDE Configuring pBlazIDE for the PicoBlaze Microcontroller4Example of How Kcpsm Source Code Converts to pBlazIDE Code Importing KCPSM3 Code into pBlazIDEFunction KCPSM3 Directive PBlazIDE Directive Differences Between the KCPSM3 Assembler and pBlazIDEDirectives Differences Between the KCPSM3 Assembler and pBlazIDEPicoBlaze Development Tools KCPSM3 Module Using the PicoBlaze Microcontroller in an Fpga DesignVhdl Design Flow Using the PicoBlaze Microcontroller in an Fpga Design Connecting the Program ROMBlack Box Instantiation of KCPSM3 using KCPSM3.ngc Black Box Instantiation of KCPSM3 using KCPSM3.ngcGenerating the Program ROM using progrom.coe Generating an ESC Schematic SymbolUsing the PicoBlaze Microcontroller in an Fpga Design Naming or Aliasing Registers Assembler DirectivesLocating Code at a Specific Address PBlazIDE Defining ConstantsNaming the Program ROM Output File Defining I/O Ports pBlazIDEDefining I/O Ports pBlazIDE Input PortsOutput Ports 5Example of pBlazIDE Dsout Directive Input/Output PortsCustom Instruction Op-Codes Custom Instruction Op-CodesAssembler Directives Simulating PicoBlaze Code Instruction Set Simulation with pBlazIDE Edit Simulator Control ButtonsInstruction Set Simulation with pBlazIDE 2pBlazIDE Simulator Control Buttons Function AssemblePause RunStep Over Run to CursorTurbocharging Simulation using FPGAs Turbocharging Simulation using FPGAsSimulating PicoBlaze Code Related Materials and References Chapter Related Materials and References KCPSM3 Syntax Example Program TemplatesAppendix Example Program Templates PBlazIDE SyntaxADD sX, Operand -Add Operand to Register sX PicoBlaze Instruction Set and Event ReferenceAppendix PicoBlaze Instruction Set and Event Reference Addcy sX, Operand -Add Operand to Register sX with CarrySX, Operand Logical Bitwise and Register sX with Operand SX, Operand Logical Bitwise and Register sX with OperandExamples Table C-1CALL Instruction Conditions Description ConditionFigure C-4COMPARE Operation Compare sX, Operand Compare Operand with Register sXDisable Interrupt Disable External Interrupt Input Disable Interrupt Disable External Interrupt InputEnable Interrupt Enable External Interrupt Input KCPSM3 Instruction PBlazIDE Instruction Figure C-5FETCH OperationPortid Å Operand SX Å Inport PC Å PC + Interrupt Event, When Enabled Table C-2JUMP Instruction Conditions Description Load sX, Operand Load Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with OperandFigure C-7OUTPUT Operation and Fpga Interface Logic Table C-3PicoBlaze Reset Values Resource Reset Event Effect Reset EventReset Event Table C-4RETURN Instruction Conditions Description PBlazIDE Equivalent RET, RET C, RET NC, RET Z, RET NZ Table C-6Rotate Right RR Operation RL sX Rotate Left Register sXRR sX Rotate Right Register sX Table C-5Rotate Left RL OperationTable C-7Shift Left Operations SL 0 1 X a sX Shift Left Register sXSL 0 1 X a sX Shift Left Register sX SR 0 1 X a sX Shift Right Register sX Shift Right with ‘ 0’ fill Figure C-8STORE Operation Store sX, sY SUB sX, Operand -Subtract Operand from Register sXFigure C-10SUBCY Instruction Registers sX Flags CARRY, Zero PBlazIDE Equivalent Subc Figure C-11ZERO Flag Logic for Test Instruction PicoBlaze 8-bit Embedded Microcontroller 117 XOR sX, Operand Logical Bitwise XOR Register sX with Operand Table D-1PicoBlaze Instruction Codes Instruction CodesJump Z PicoBlaze 8-bit Embedded Microcontroller 121 Appendix Instruction Codes Reg Description Register and Scratchpad RAM Planning WorksheetsRegisters Loc Description Scratchpad RAMAppendix Register and Scratchpad RAM Planning Worksheets