Manuals / Xilinx / Communications / Answering Machine

Xilinx UG129 manual Load sX, Operand Load Register sX with Operand

Models: UG129

1 124

Download 124 pages 29.5 Kb

Page 102

R

Appendix : PicoBlaze Instruction Set and Event Reference

LOAD sX, Operand — Load Register sX with Operand

The LOAD instruction loads the contents of any register. The new value is either the contents of any other register or an immediate constant. The LOAD instruction has no effect on the status flags.

Because the LOAD instruction does not affect the flags, use it to reorder and assign register contents at any stage of the program execution. Loading a constant into a register via the LOAD instruction has no impact on program size or performance and is the easiest method to assign a value or to clear a register.

Examples

LOAD sX, sY; Move the contents of register sY to register sX

LOAD sX, kk; Load register sX with the immediate constant kk

Pseudocode

sX Å Operand

PC Å PC + 1

Registers/Flags Altered

Registers: sX, PC

Flags: Not affected

102	www.xilinx.com	PicoBlaze 8-bit Embedded Microcontroller
		UG129 (v1.1.2) June 24, 2008

Image 102

Xilinx UG129 manual Load sX, Operand Load Register sX with Operand

Contents

PicoBlaze 8-bit Embedded Microcontroller User Guide UG129 v1.1.2 June 24Revision History Version RevisionLimitation of Liability Limited Warranty and DisclaimerLimitations Technical Support LimitationsAcknowledgments Preface AcknowledgmentsGuide Contents About This GuidePreface About This Guide Table of Contents Interrupts Performance Appendix C PicoBlaze Instruction Set and Event Reference PicoBlaze Microcontroller Features IntroductionInstruction Program Store PicoBlaze Microcontroller Functional BlocksGeneral-Purpose Registers IntroductionByte Scratchpad RAM Arithmetic Logic Unit ALUFlags Input/OutputProgram Flow Control ResetProgram Counter PC CALL/RETURN StackWhy the PicoBlaze Microcontroller? Why Use a Microcontroller within an FPGA?Why the PicoBlaze Microcontroller? Strengths WeaknessesPicoBlaze Interface Signals PicoBlaze Interface Signal DescriptionsSignal Direction Description Readstrobe PicoBlaze Instruction Set 1PicoBlaze Instruction Set alphabetical listingEnable Interrupt Returni Disable Address Spaces Instruction 1Kx18 Direct Processing Data Logic InstructionsPicoBlaze Instruction Set 2Complementing a Register Value 3Inverting an Individual Bit Location616-Setting a Bit Location Arithmetic InstructionsSUB and Subcy Subtract Instructions Multiplication 10Incrementing and Decrementing a Register148-bit by 8-bit Multiply Routine Produces a 16-bit Product 168-bit by 8-bit Multiply Routine Using Hardware Multiplier DivisionNo Operation NOP 18Loading a Register with Itself Acts as a NOP InstructionSetting and Clearing Carry Flag Test and Compare22The Test Instruction Affects the Zero Flag 25Generate Parity for a Register Using the Test Instruction Shift and Rotate InstructionsSRX 5PicoBlaze Rotate Instructions Rotate Left Rotate RightMoving Data Program Flow ControlProgram Flow Control 6Instruction Conditional Execution DescriptionCALL/RETURN Program Flow Control UG129 v1.1.2 June 24 Interrupts 1Simple Interrupt LogicExample Interrupt Flow 2Example Interrupt Flow3Interrupt Timing Diagram Example Interrupt FlowInterrupts Direct Addressing Scratchpad RAMAddress Modes Indirect AddressingImplementing a Look-Up Table Scratchpad RAMStack Operations Fifo OperationsStack Operations Scratchpad RAM Input and Output Ports Portid PortInput Operations 1INPUT Operation and Fpga Interface LogicINPORT70 Input OperationsPORTID70 Register s0Applications with Few Input Sources Readstrobe Interaction with FIFOsInput and Output Ports Output Operations Output OperationsSimple Output Structure for Few Output Destinations Fpga Register8Use Constant Directives to Declare Output Port Addresses Pipelining for Maximum Performance 9Pipelining the Portid Decoding Improves PerformancePipelining for Maximum Performance Repartitioning the Design for Maximum Performance Effective Pipelining Improves Read PerformanceInstruction Storage Configurations Standard Configuration Single 1Kx18 Block RAMInstruction Storage Configurations Two PicoBlaze Microcontrollers Share a 1Kx18 Code Image6Using Distributed ROM for Instruction Memory Distributed ROM Instead of Block RAMInstruction Storage Configurations Predicting Executing Performance PerformanceInput Clock Frequency FrequencyPerformance PicoBlaze Development Tools AssemblerAssembly Errors Input and Output FilesPicoBlaze Development Tools Configuring pBlazIDE for the PicoBlaze Microcontroller Mediatronix pBlazIDEImporting KCPSM3 Code into pBlazIDE 4Example of How Kcpsm Source Code Converts to pBlazIDE CodeDifferences Between the KCPSM3 Assembler and pBlazIDE Differences Between the KCPSM3 Assembler and pBlazIDEDirectives Function KCPSM3 Directive PBlazIDE DirectivePicoBlaze Development Tools Using the PicoBlaze Microcontroller in an Fpga Design Vhdl Design FlowKCPSM3 Module Connecting the Program ROM Using the PicoBlaze Microcontroller in an Fpga DesignGenerating an ESC Schematic Symbol Black Box Instantiation of KCPSM3 using KCPSM3.ngcGenerating the Program ROM using progrom.coe Black Box Instantiation of KCPSM3 using KCPSM3.ngcUsing the PicoBlaze Microcontroller in an Fpga Design Assembler Directives Locating Code at a Specific AddressNaming or Aliasing Registers Defining I/O Ports pBlazIDE Defining ConstantsNaming the Program ROM Output File PBlazIDEInput Ports Output PortsDefining I/O Ports pBlazIDE Input/Output Ports 5Example of pBlazIDE Dsout DirectiveCustom Instruction Op-Codes Custom Instruction Op-CodesAssembler Directives Simulating PicoBlaze Code Instruction Set Simulation with pBlazIDE 2pBlazIDE Simulator Control Buttons Function Assemble Simulator Control ButtonsInstruction Set Simulation with pBlazIDE EditRun to Cursor RunStep Over PauseTurbocharging Simulation using FPGAs Turbocharging Simulation using FPGAsSimulating PicoBlaze Code Related Materials and References Chapter Related Materials and References Example Program Templates KCPSM3 SyntaxPBlazIDE Syntax Appendix Example Program TemplatesPicoBlaze Instruction Set and Event Reference ADD sX, Operand -Add Operand to Register sXAddcy sX, Operand -Add Operand to Register sX with Carry Appendix PicoBlaze Instruction Set and Event ReferenceSX, Operand Logical Bitwise and Register sX with Operand SX, Operand Logical Bitwise and Register sX with OperandExamples Condition Table C-1CALL Instruction Conditions DescriptionCompare sX, Operand Compare Operand with Register sX Figure C-4COMPARE OperationDisable Interrupt Disable External Interrupt Input Enable Interrupt Enable External Interrupt InputDisable Interrupt Disable External Interrupt Input Figure C-5FETCH Operation KCPSM3 Instruction PBlazIDE InstructionPortid Å Operand SX Å Inport PC Å PC + Interrupt Event, When Enabled Table C-2JUMP Instruction Conditions Description Load sX, Operand Load Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with OperandFigure C-7OUTPUT Operation and Fpga Interface Logic Reset Event Reset EventTable C-3PicoBlaze Reset Values Resource Reset Event Effect Table C-4RETURN Instruction Conditions Description PBlazIDE Equivalent RET, RET C, RET NC, RET Z, RET NZ Table C-5Rotate Left RL Operation RL sX Rotate Left Register sXRR sX Rotate Right Register sX Table C-6Rotate Right RR OperationSL 0 1 X a sX Shift Left Register sX SL 0 1 X a sX Shift Left Register sXTable C-7Shift Left Operations SR 0 1 X a sX Shift Right Register sX Shift Right with ‘ 0’ fill Figure C-8STORE Operation SUB sX, Operand -Subtract Operand from Register sX Store sX, sYFigure C-10SUBCY Instruction Registers sX Flags CARRY, Zero PBlazIDE Equivalent Subc Figure C-11ZERO Flag Logic for Test Instruction PicoBlaze 8-bit Embedded Microcontroller 117 XOR sX, Operand Logical Bitwise XOR Register sX with Operand Instruction Codes Table D-1PicoBlaze Instruction CodesJump Z PicoBlaze 8-bit Embedded Microcontroller 121 Appendix Instruction Codes Register and Scratchpad RAM Planning Worksheets RegistersReg Description Scratchpad RAM Appendix Register and Scratchpad RAM Planning WorksheetsLoc Description