Xilinx UG129 PicoBlaze Microcontroller Functional Blocks, General-Purpose Registers, Introduction

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Chapter 1: Introduction

•Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags

•64-byte internal scratchpad RAM

•256 input and 256 output ports for easy expansion and enhancement

•Automatic 31-location CALL/RETURN stack

•Predictable performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex-II Pro FPGA

•Fast interrupt response; worst-case 5 clock cycles

•Optimized for Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGA architectures—just 96 slices and 0.5 to 1 block RAM

•Assembler, instruction-set simulator support

1Kx18

ProgramCounter

(PC)

31x10

CALL/RETURN

Stack

64-Byte

PORT_ID

Instruction

Scratchpad RAM

PROM

OUT_PORT

Instruction

Flags

Constants

Z

Zero

Decoder

C

Carry

INTERRUPT

16 Byte-Wide Registers

Enable

Operand 1

ALU

IE

s0

s1

s2

s3

s4

s5

s6

s7

IN_PORT

s8

s9

sA

sB

sC

sD

sE

sF

Operand 2

UG129_c1_01_051204

Figure 1-1:PicoBlaze Embedded Microcontroller Block Diagram

PicoBlaze Microcontroller Functional Blocks

General-Purpose Registers

The PicoBlaze microcontroller includes 16 byte-wide general-purpose registers, designated as registers s0 through sF. For better program clarity, registers can be renamed using an assembler directive. All register operations are completely interchangeable; no registers are reserved for special tasks or have priority over any other register. There is no dedicated accumulator; each result is computed in a specified register.

1,024-Instruction Program Store

The PicoBlaze microcontroller executes up to 1,024 instructions from memory within the FPGA, typically from a single block RAM. Each PicoBlaze instruction is 18 bits wide. The instructions are compiled within the FPGA design and automatically loaded during the FPGA configuration process.

12 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller

UG129 (v1.1.2) June 24, 2008