PicoBlaze Instruction Set | Xilinx UG129 guide

R

Chapter 3

PicoBlaze Instruction Set

Table 3-1summarizes the entire PicoBlaze™ processor instruction set, which appears alphabetically. Instructions are listed using the KCPSM3 syntax. If different, the pBlazIDE syntax appears in parentheses. Each instruction includes an overview description, a functional description, and how the ZERO and CARRY flags are affected. For more details on each instruction, see Appendix C, “PicoBlaze Instruction Set and Event Reference.”

Table 3-1:PicoBlaze Instruction Set (alphabetical listing)

Instruction	Description	Function	ZERO	CARRY

ADD sX, kk	Add register sX with literal kk	sX Å sX + kk	?	?

ADD sX, sY	Add register sX with register sY	sX Å sX + sY	?	?

ADDCY sX, kk	Add register sX with literal kk with	sX Å sX + kk + CARRY	?	?
(ADDC)	CARRY bit

ADDCY sX, sY	Add register sX with register sY with	sX Å sX + sY + CARRY	?	?
(ADDC)	CARRY bit

AND sX, kk	Bitwise AND register sX with literal kk	sX Å sX AND kk	?	0

AND sX, sY	Bitwise AND register sX with register sY	sX Å sX AND sY	?	0

CALL aaa	Unconditionally call subroutine at aaa	TOS Å PC	-	-
		PC Å aaa

CALL C, aaa	If CARRY flag set, call subroutine at aaa	If CARRY=1, {TOS Å PC,	-	-
		PC Å aaa}

CALL NC, aaa	If CARRY flag not set, call subroutine at	If CARRY=0, {TOS Å PC,	-	-
	aaa	PC Å aaa}

CALL NZ, aaa	If ZERO flag not set, call subroutine at aaa	If ZERO=0, {TOS Å PC,	-	-
		PC Å aaa}

CALL Z, aaa	If ZERO flag set, call subroutine at aaa	If ZERO=1, {TOS Å PC,	-	-
		PC Å aaa}

COMPARE sX, kk	Compare register sX with literal kk. Set	If sX=kk, ZERO Å 1	?	?
(COMP)	CARRY and ZERO flags as appropriate.	If sX<kk, CARRY Å 1
	Registers are unaffected.	If sX<kk, CARRY Å 1
	Registers are unaffected.

COMPARE sX, sY	Compare register sX with register sY. Set	If sX=sY, ZERO Å 1	?	?
(COMP)	CARRY and ZERO flags as appropriate.	If sX<sY, CARRY Å 1
	Registers are unaffected.	If sX<sY, CARRY Å 1
	Registers are unaffected.

DISABLE INTERRUPT	Disable interrupt input	INTERRUPT_ENABLE Å 0	-	-
(DINT)

PicoBlaze 8-bit Embedded Microcontroller

www.xilinx.com

19

UG129 (v1.1.2) June 24, 2008

Image 19

Xilinx UG129 manual 1PicoBlaze Instruction Set alphabetical listing

Contents

UG129 v1.1.2 June 24 PicoBlaze 8-bit Embedded Microcontroller User Guide Version Revision Revision History Technical Support Limitations Limited Warranty and DisclaimerLimitations Limitation of Liability Preface Acknowledgments Acknowledgments About This Guide Guide Contents Preface About This Guide Table of Contents Interrupts Performance Appendix C PicoBlaze Instruction Set and Event Reference Introduction PicoBlaze Microcontroller Features Introduction PicoBlaze Microcontroller Functional BlocksGeneral-Purpose Registers Instruction Program Store Input/Output Arithmetic Logic Unit ALUFlags Byte Scratchpad RAM CALL/RETURN Stack ResetProgram Counter PC Program Flow Control Why Use a Microcontroller within an FPGA? Why the PicoBlaze Microcontroller?Why the PicoBlaze Microcontroller? Weaknesses Strengths PicoBlaze Interface Signal Descriptions PicoBlaze Interface SignalsSignal Direction Description Readstrobe 1PicoBlaze Instruction Set alphabetical listing PicoBlaze Instruction Set Enable Interrupt Returni Disable Address Spaces Instruction 1Kx18 Direct Logic Instructions Processing DataPicoBlaze Instruction Set 3Inverting an Individual Bit Location 2Complementing a Register Value Arithmetic Instructions 616-Setting a Bit Location SUB and Subcy Subtract Instructions 10Incrementing and Decrementing a Register Multiplication 148-bit by 8-bit Multiply Routine Produces a 16-bit Product Division 168-bit by 8-bit Multiply Routine Using Hardware Multiplier 18Loading a Register with Itself Acts as a NOP Instruction No Operation NOP Test and Compare Setting and Clearing Carry Flag 22The Test Instruction Affects the Zero Flag Shift and Rotate Instructions 25Generate Parity for a Register Using the Test Instruction 5PicoBlaze Rotate Instructions Rotate Left Rotate Right SRX Program Flow Control Moving Data 6Instruction Conditional Execution Description Program Flow Control CALL/RETURN Program Flow Control UG129 v1.1.2 June 24 1Simple Interrupt Logic Interrupts 2Example Interrupt Flow Example Interrupt Flow Example Interrupt Flow 3Interrupt Timing Diagram Interrupts Indirect Addressing Scratchpad RAMAddress Modes Direct Addressing Scratchpad RAM Implementing a Look-Up Table Fifo Operations Stack OperationsStack Operations Scratchpad RAM Portid Port Input and Output Ports 1INPUT Operation and Fpga Interface Logic Input Operations Register s0 Input OperationsPORTID70 INPORT70 Readstrobe Interaction with FIFOs Applications with Few Input SourcesInput and Output Ports Output Operations Output Operations Fpga Register Simple Output Structure for Few Output Destinations 8Use Constant Directives to Declare Output Port Addresses 9Pipelining the Portid Decoding Improves Performance Pipelining for Maximum Performance Pipelining for Maximum Performance Effective Pipelining Improves Read Performance Repartitioning the Design for Maximum Performance Standard Configuration Single 1Kx18 Block RAM Instruction Storage Configurations Two PicoBlaze Microcontrollers Share a 1Kx18 Code Image Instruction Storage Configurations Distributed ROM Instead of Block RAM 6Using Distributed ROM for Instruction Memory Instruction Storage Configurations Frequency PerformanceInput Clock Frequency Predicting Executing Performance Performance Assembler PicoBlaze Development Tools Input and Output Files Assembly ErrorsPicoBlaze Development Tools Mediatronix pBlazIDE Configuring pBlazIDE for the PicoBlaze Microcontroller 4Example of How Kcpsm Source Code Converts to pBlazIDE Code Importing KCPSM3 Code into pBlazIDE Function KCPSM3 Directive PBlazIDE Directive Differences Between the KCPSM3 Assembler and pBlazIDEDirectives Differences Between the KCPSM3 Assembler and pBlazIDE PicoBlaze Development Tools Vhdl Design Flow Using the PicoBlaze Microcontroller in an Fpga DesignKCPSM3 Module Using the PicoBlaze Microcontroller in an Fpga Design Connecting the Program ROM Black Box Instantiation of KCPSM3 using KCPSM3.ngc Black Box Instantiation of KCPSM3 using KCPSM3.ngcGenerating the Program ROM using progrom.coe Generating an ESC Schematic Symbol Using the PicoBlaze Microcontroller in an Fpga Design Locating Code at a Specific Address Assembler DirectivesNaming or Aliasing Registers PBlazIDE Defining ConstantsNaming the Program ROM Output File Defining I/O Ports pBlazIDE Output Ports Input PortsDefining I/O Ports pBlazIDE 5Example of pBlazIDE Dsout Directive Input/Output Ports Custom Instruction Op-Codes Custom Instruction Op-Codes Assembler Directives Simulating PicoBlaze Code Instruction Set Simulation with pBlazIDE Edit Simulator Control ButtonsInstruction Set Simulation with pBlazIDE 2pBlazIDE Simulator Control Buttons Function Assemble Pause RunStep Over Run to Cursor Turbocharging Simulation using FPGAs Turbocharging Simulation using FPGAs Simulating PicoBlaze Code Related Materials and References Chapter Related Materials and References KCPSM3 Syntax Example Program Templates Appendix Example Program Templates PBlazIDE Syntax ADD sX, Operand -Add Operand to Register sX PicoBlaze Instruction Set and Event Reference Appendix PicoBlaze Instruction Set and Event Reference Addcy sX, Operand -Add Operand to Register sX with Carry SX, Operand Logical Bitwise and Register sX with Operand SX, Operand Logical Bitwise and Register sX with Operand Examples Table C-1CALL Instruction Conditions Description Condition Figure C-4COMPARE Operation Compare sX, Operand Compare Operand with Register sX Enable Interrupt Enable External Interrupt Input Disable Interrupt Disable External Interrupt InputDisable Interrupt Disable External Interrupt Input KCPSM3 Instruction PBlazIDE Instruction Figure C-5FETCH Operation Portid Å Operand SX Å Inport PC Å PC + Interrupt Event, When Enabled Table C-2JUMP Instruction Conditions Description Load sX, Operand Load Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Figure C-7OUTPUT Operation and Fpga Interface Logic Reset Event Reset EventTable C-3PicoBlaze Reset Values Resource Reset Event Effect Table C-4RETURN Instruction Conditions Description PBlazIDE Equivalent RET, RET C, RET NC, RET Z, RET NZ Table C-6Rotate Right RR Operation RL sX Rotate Left Register sXRR sX Rotate Right Register sX Table C-5Rotate Left RL Operation SL 0 1 X a sX Shift Left Register sX SL 0 1 X a sX Shift Left Register sXTable C-7Shift Left Operations SR 0 1 X a sX Shift Right Register sX Shift Right with ‘ 0’ fill Figure C-8STORE Operation Store sX, sY SUB sX, Operand -Subtract Operand from Register sX Figure C-10SUBCY Instruction Registers sX Flags CARRY, Zero PBlazIDE Equivalent Subc Figure C-11ZERO Flag Logic for Test Instruction PicoBlaze 8-bit Embedded Microcontroller 117 XOR sX, Operand Logical Bitwise XOR Register sX with Operand Table D-1PicoBlaze Instruction Codes Instruction Codes Jump Z PicoBlaze 8-bit Embedded Microcontroller 121 Appendix Instruction Codes Registers Register and Scratchpad RAM Planning WorksheetsReg Description Appendix Register and Scratchpad RAM Planning Worksheets Scratchpad RAMLoc Description