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Chapter 12: Simulating PicoBlaze Code
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Reset | Reset the simulator. Reset the Program Counter (PC) and Stack Pointer (SP). Register and | ||
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| RAM values are not reset. |
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Run | Run the program. The program continues running until an active breakpoint is | ||
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| encountered or if the Reset or Pause button is pressed. |
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| Execute a single instruction. The active register, memory, and I/O displays are updated |
Single Step | and the cursor arrow advances to the next instruction. The next instruction to be executed | ||
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| is highlighted in blue and a blue arrow appears to the left of the instruction line. After |
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| executing an instruction, the code coverage indicator changes from blue to green. If |
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| executing a valid CALL instruction, the program steps into the subroutine function. |
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Step Over | Behaves like the Single Step button except that the simulator does not step into CALL | ||
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| instructions. If executing a valid CALL instruction, the program executes the entire |
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| subroutine and the display advances to the instruction following the CALL instruction. |
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Run to Cursor | Run the program until the program advances to the current cursor location. | ||
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Pause | Pause a running simulation and display the current state of the PicoBlaze microcontroller. | ||
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| Continue the simulation using any of the green action buttons. |
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Toggle Breakpoint | Set or remove a breakpoint on the instruction at the current cursor location. The instruction | ||
line is highlighted in red and a breakpoint indicator appears to the left of the line. Multiple | |||
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| breakpoints may be simultaneously active. If the simulation reaches an instruction with an |
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| active breakpoint, the simulation automatically pauses. |
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Remove All | Clear all active breakpoints. | ||
Breakpoints |
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Using the pBlazIDE Instruction Set Simulator with KCPSM3 Programs
The pBlazIDE software primarily supports only a VHDL design flow, which is sufficient for many applications. The KCPSM3 assembler supports Verilog, black box, and Xilinx System Generator design flows in addition to the VHDL flow.
Fortunately, pBlazIDE has an import function that translates a
Simulating FPGA Interaction with the pBlazIDE Instruction Set Simulator
Although pBlazIDE does not simulate FPGA logic, it does provide basic capabilities to test the PicoBlaze INPUT and OUTPUT operations that connect to FPGA logic. The DSIN, DSOUT, and DSIO directives declare input and output ports, and also provide simple file I/O functions. A stimulus file associated with a DSIN statement simulates data reads during a PicoBlaze INPUT operation. Similarly, the DSOUT statement specifies an output file where PicoBlaze OUTPUT operations are recorded.
84 | www.xilinx.com | PicoBlaze |
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| UG129 (v1.1.2) June 24, 2008 |
