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Xilinx UG129 manual Appendix Register and Scratchpad RAM Planning Worksheets, Loc Description

Models: UG129

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Appendix : Register and Scratchpad RAM Planning Worksheets

Scratchpad RAM

Loc.	Description	Loc.	Description

00		20

01		21

02		22

03		23

04		24

05		25

06		26

07		27

08		28

09		29

0A		2A

0B		2B

0C		2C

0D		2D

0E		2E

0F		2F

10		30

11		31

12		32

13		33

14		34

15		35

16		36

17		37

18		38

19		39

1A		3A

1B		3B

1C		3C

1D		3D

1E		3E

1F		3F

124	www.xilinx.com	PicoBlaze 8-bit Embedded Microcontroller
		UG129 (v1.1.2) June 24, 2008

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Xilinx UG129 manual Appendix Register and Scratchpad RAM Planning Worksheets, Loc Description

Contents

PicoBlaze 8-bit Embedded Microcontroller User Guide UG129 v1.1.2 June 24Revision History Version RevisionLimited Warranty and Disclaimer LimitationsLimitation of Liability Technical Support LimitationsAcknowledgments Preface AcknowledgmentsGuide Contents About This GuidePreface About This Guide Table of Contents Interrupts Performance Appendix C PicoBlaze Instruction Set and Event Reference PicoBlaze Microcontroller Features IntroductionPicoBlaze Microcontroller Functional Blocks General-Purpose RegistersInstruction Program Store IntroductionArithmetic Logic Unit ALU FlagsByte Scratchpad RAM Input/OutputReset Program Counter PCProgram Flow Control CALL/RETURN StackWhy Use a Microcontroller within an FPGA? Why the PicoBlaze Microcontroller?Why the PicoBlaze Microcontroller? Strengths WeaknessesPicoBlaze Interface Signal Descriptions PicoBlaze Interface SignalsSignal Direction Description Readstrobe PicoBlaze Instruction Set 1PicoBlaze Instruction Set alphabetical listingEnable Interrupt Returni Disable Address Spaces Instruction 1Kx18 Direct Logic Instructions Processing DataPicoBlaze Instruction Set 2Complementing a Register Value 3Inverting an Individual Bit Location616-Setting a Bit Location Arithmetic InstructionsSUB and Subcy Subtract Instructions Multiplication 10Incrementing and Decrementing a Register148-bit by 8-bit Multiply Routine Produces a 16-bit Product 168-bit by 8-bit Multiply Routine Using Hardware Multiplier DivisionNo Operation NOP 18Loading a Register with Itself Acts as a NOP InstructionSetting and Clearing Carry Flag Test and Compare22The Test Instruction Affects the Zero Flag 25Generate Parity for a Register Using the Test Instruction Shift and Rotate InstructionsSRX 5PicoBlaze Rotate Instructions Rotate Left Rotate RightMoving Data Program Flow ControlProgram Flow Control 6Instruction Conditional Execution DescriptionCALL/RETURN Program Flow Control UG129 v1.1.2 June 24 Interrupts 1Simple Interrupt LogicExample Interrupt Flow 2Example Interrupt Flow3Interrupt Timing Diagram Example Interrupt FlowInterrupts Scratchpad RAM Address ModesDirect Addressing Indirect AddressingImplementing a Look-Up Table Scratchpad RAMFifo Operations Stack OperationsStack Operations Scratchpad RAM Input and Output Ports Portid PortInput Operations 1INPUT Operation and Fpga Interface LogicInput Operations PORTID70INPORT70 Register s0Readstrobe Interaction with FIFOs Applications with Few Input SourcesInput and Output Ports Output Operations Output OperationsSimple Output Structure for Few Output Destinations Fpga Register8Use Constant Directives to Declare Output Port Addresses Pipelining for Maximum Performance 9Pipelining the Portid Decoding Improves PerformancePipelining for Maximum Performance Repartitioning the Design for Maximum Performance Effective Pipelining Improves Read PerformanceInstruction Storage Configurations Standard Configuration Single 1Kx18 Block RAMInstruction Storage Configurations Two PicoBlaze Microcontrollers Share a 1Kx18 Code Image6Using Distributed ROM for Instruction Memory Distributed ROM Instead of Block RAMInstruction Storage Configurations Performance Input Clock FrequencyPredicting Executing Performance FrequencyPerformance PicoBlaze Development Tools AssemblerInput and Output Files Assembly ErrorsPicoBlaze Development Tools Configuring pBlazIDE for the PicoBlaze Microcontroller Mediatronix pBlazIDEImporting KCPSM3 Code into pBlazIDE 4Example of How Kcpsm Source Code Converts to pBlazIDE CodeDifferences Between the KCPSM3 Assembler and pBlazIDE DirectivesDifferences Between the KCPSM3 Assembler and pBlazIDE Function KCPSM3 Directive PBlazIDE DirectivePicoBlaze Development Tools Vhdl Design Flow Using the PicoBlaze Microcontroller in an Fpga DesignKCPSM3 Module Connecting the Program ROM Using the PicoBlaze Microcontroller in an Fpga DesignBlack Box Instantiation of KCPSM3 using KCPSM3.ngc Generating the Program ROM using progrom.coeGenerating an ESC Schematic Symbol Black Box Instantiation of KCPSM3 using KCPSM3.ngcUsing the PicoBlaze Microcontroller in an Fpga Design Locating Code at a Specific Address Assembler DirectivesNaming or Aliasing Registers Defining Constants Naming the Program ROM Output FileDefining I/O Ports pBlazIDE PBlazIDEOutput Ports Input PortsDefining I/O Ports pBlazIDE Input/Output Ports 5Example of pBlazIDE Dsout DirectiveCustom Instruction Op-Codes Custom Instruction Op-CodesAssembler Directives Simulating PicoBlaze Code Instruction Set Simulation with pBlazIDE Simulator Control Buttons Instruction Set Simulation with pBlazIDE2pBlazIDE Simulator Control Buttons Function Assemble EditRun Step OverRun to Cursor PauseTurbocharging Simulation using FPGAs Turbocharging Simulation using FPGAsSimulating PicoBlaze Code Related Materials and References Chapter Related Materials and References Example Program Templates KCPSM3 SyntaxPBlazIDE Syntax Appendix Example Program TemplatesPicoBlaze Instruction Set and Event Reference ADD sX, Operand -Add Operand to Register sXAddcy sX, Operand -Add Operand to Register sX with Carry Appendix PicoBlaze Instruction Set and Event ReferenceSX, Operand Logical Bitwise and Register sX with Operand SX, Operand Logical Bitwise and Register sX with OperandExamples Condition Table C-1CALL Instruction Conditions DescriptionCompare sX, Operand Compare Operand with Register sX Figure C-4COMPARE OperationEnable Interrupt Enable External Interrupt Input Disable Interrupt Disable External Interrupt InputDisable Interrupt Disable External Interrupt Input Figure C-5FETCH Operation KCPSM3 Instruction PBlazIDE InstructionPortid Å Operand SX Å Inport PC Å PC + Interrupt Event, When Enabled Table C-2JUMP Instruction Conditions Description Load sX, Operand Load Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with OperandFigure C-7OUTPUT Operation and Fpga Interface Logic Reset Event Reset EventTable C-3PicoBlaze Reset Values Resource Reset Event Effect Table C-4RETURN Instruction Conditions Description PBlazIDE Equivalent RET, RET C, RET NC, RET Z, RET NZ RL sX Rotate Left Register sX RR sX Rotate Right Register sXTable C-5Rotate Left RL Operation Table C-6Rotate Right RR OperationSL 0 1 X a sX Shift Left Register sX SL 0 1 X a sX Shift Left Register sXTable C-7Shift Left Operations SR 0 1 X a sX Shift Right Register sX Shift Right with ‘ 0’ fill Figure C-8STORE Operation SUB sX, Operand -Subtract Operand from Register sX Store sX, sYFigure C-10SUBCY Instruction Registers sX Flags CARRY, Zero PBlazIDE Equivalent Subc Figure C-11ZERO Flag Logic for Test Instruction PicoBlaze 8-bit Embedded Microcontroller 117 XOR sX, Operand Logical Bitwise XOR Register sX with Operand Instruction Codes Table D-1PicoBlaze Instruction CodesJump Z PicoBlaze 8-bit Embedded Microcontroller 121 Appendix Instruction Codes Registers Register and Scratchpad RAM Planning WorksheetsReg Description Appendix Register and Scratchpad RAM Planning Worksheets Scratchpad RAMLoc Description