PicoBlaze 8-bit Embedded Microcontroller User Guide
UG129 v1.1.2 June 24
Revision History
Version Revision
Limitation of Liability
Limited Warranty and Disclaimer
Limitations
Technical Support Limitations
Acknowledgments
Preface Acknowledgments
Guide Contents
About This Guide
Preface About This Guide
Table of Contents
Interrupts
Performance
Appendix C PicoBlaze Instruction Set and Event Reference
PicoBlaze Microcontroller Features
Introduction
Instruction Program Store
PicoBlaze Microcontroller Functional Blocks
General-Purpose Registers
Introduction
Byte Scratchpad RAM
Arithmetic Logic Unit ALU
Flags
Input/Output
Program Flow Control
Reset
Program Counter PC
CALL/RETURN Stack
Why Use a Microcontroller within an FPGA?
Why the PicoBlaze Microcontroller?
Why the PicoBlaze Microcontroller?
Strengths
Weaknesses
PicoBlaze Interface Signal Descriptions
PicoBlaze Interface Signals
Signal Direction Description
Readstrobe
PicoBlaze Instruction Set
1PicoBlaze Instruction Set alphabetical listing
Enable Interrupt
Returni Disable
Address Spaces
Instruction 1Kx18 Direct
Logic Instructions
Processing Data
PicoBlaze Instruction Set
2Complementing a Register Value
3Inverting an Individual Bit Location
616-Setting a Bit Location
Arithmetic Instructions
SUB and Subcy Subtract Instructions
Multiplication
10Incrementing and Decrementing a Register
148-bit by 8-bit Multiply Routine Produces a 16-bit Product
168-bit by 8-bit Multiply Routine Using Hardware Multiplier
Division
No Operation NOP
18Loading a Register with Itself Acts as a NOP Instruction
Setting and Clearing Carry Flag
Test and Compare
22The Test Instruction Affects the Zero Flag
25Generate Parity for a Register Using the Test Instruction
Shift and Rotate Instructions
SRX
5PicoBlaze Rotate Instructions Rotate Left Rotate Right
Moving Data
Program Flow Control
Program Flow Control
6Instruction Conditional Execution Description
CALL/RETURN
Program Flow Control
UG129 v1.1.2 June 24
Interrupts
1Simple Interrupt Logic
Example Interrupt Flow
2Example Interrupt Flow
3Interrupt Timing Diagram
Example Interrupt Flow
Interrupts
Direct Addressing
Scratchpad RAM
Address Modes
Indirect Addressing
Implementing a Look-Up Table
Scratchpad RAM
Fifo Operations
Stack Operations
Stack Operations
Scratchpad RAM
Input and Output Ports
Portid Port
Input Operations
1INPUT Operation and Fpga Interface Logic
INPORT70
Input Operations
PORTID70
Register s0
Readstrobe Interaction with FIFOs
Applications with Few Input Sources
Input and Output Ports
Output Operations
Output Operations
Simple Output Structure for Few Output Destinations
Fpga Register
8Use Constant Directives to Declare Output Port Addresses
Pipelining for Maximum Performance
9Pipelining the Portid Decoding Improves Performance
Pipelining for Maximum Performance
Repartitioning the Design for Maximum Performance
Effective Pipelining Improves Read Performance
Instruction Storage Configurations
Standard Configuration Single 1Kx18 Block RAM
Instruction Storage Configurations
Two PicoBlaze Microcontrollers Share a 1Kx18 Code Image
6Using Distributed ROM for Instruction Memory
Distributed ROM Instead of Block RAM
Instruction Storage Configurations
Predicting Executing Performance
Performance
Input Clock Frequency
Frequency
Performance
PicoBlaze Development Tools
Assembler
Input and Output Files
Assembly Errors
PicoBlaze Development Tools
Configuring pBlazIDE for the PicoBlaze Microcontroller
Mediatronix pBlazIDE
Importing KCPSM3 Code into pBlazIDE
4Example of How Kcpsm Source Code Converts to pBlazIDE Code
Differences Between the KCPSM3 Assembler and pBlazIDE
Differences Between the KCPSM3 Assembler and pBlazIDE
Directives
Function KCPSM3 Directive PBlazIDE Directive
PicoBlaze Development Tools
Vhdl Design Flow
Using the PicoBlaze Microcontroller in an Fpga Design
KCPSM3 Module
Connecting the Program ROM
Using the PicoBlaze Microcontroller in an Fpga Design
Generating an ESC Schematic Symbol
Black Box Instantiation of KCPSM3 using KCPSM3.ngc
Generating the Program ROM using progrom.coe
Black Box Instantiation of KCPSM3 using KCPSM3.ngc
Using the PicoBlaze Microcontroller in an Fpga Design
Locating Code at a Specific Address
Assembler Directives
Naming or Aliasing Registers
Defining I/O Ports pBlazIDE
Defining Constants
Naming the Program ROM Output File
PBlazIDE
Output Ports
Input Ports
Defining I/O Ports pBlazIDE
Input/Output Ports
5Example of pBlazIDE Dsout Directive
Custom Instruction Op-Codes
Custom Instruction Op-Codes
Assembler Directives
Simulating PicoBlaze Code
Instruction Set Simulation with pBlazIDE
2pBlazIDE Simulator Control Buttons Function Assemble
Simulator Control Buttons
Instruction Set Simulation with pBlazIDE
Edit
Run to Cursor
Run
Step Over
Pause
Turbocharging Simulation using FPGAs
Turbocharging Simulation using FPGAs
Simulating PicoBlaze Code
Related Materials and References
Chapter Related Materials and References
Example Program Templates
KCPSM3 Syntax
PBlazIDE Syntax
Appendix Example Program Templates
PicoBlaze Instruction Set and Event Reference
ADD sX, Operand -Add Operand to Register sX
Addcy sX, Operand -Add Operand to Register sX with Carry
Appendix PicoBlaze Instruction Set and Event Reference
SX, Operand Logical Bitwise and Register sX with Operand
SX, Operand Logical Bitwise and Register sX with Operand
Examples
Condition
Table C-1CALL Instruction Conditions Description
Compare sX, Operand Compare Operand with Register sX
Figure C-4COMPARE Operation
Enable Interrupt Enable External Interrupt Input
Disable Interrupt Disable External Interrupt Input
Disable Interrupt Disable External Interrupt Input
Figure C-5FETCH Operation
KCPSM3 Instruction PBlazIDE Instruction
Portid Å Operand SX Å Inport PC Å PC +
Interrupt Event, When Enabled
Table C-2JUMP Instruction Conditions Description
Load sX, Operand Load Register sX with Operand
Or sX, Operand Logical Bitwise or Register sX with Operand
Or sX, Operand Logical Bitwise or Register sX with Operand
Figure C-7OUTPUT Operation and Fpga Interface Logic
Reset Event
Reset Event
Table C-3PicoBlaze Reset Values Resource Reset Event Effect
Table C-4RETURN Instruction Conditions Description
PBlazIDE Equivalent RET, RET C, RET NC, RET Z, RET NZ
Table C-5Rotate Left RL Operation
RL sX Rotate Left Register sX
RR sX Rotate Right Register sX
Table C-6Rotate Right RR Operation
SL 0 1 X a sX Shift Left Register sX
SL 0 1 X a sX Shift Left Register sX
Table C-7Shift Left Operations
SR 0 1 X a sX Shift Right Register sX
Shift Right with ‘ 0’ fill
Figure C-8STORE Operation
SUB sX, Operand -Subtract Operand from Register sX
Store sX, sY
Figure C-10SUBCY Instruction
Registers sX Flags CARRY, Zero PBlazIDE Equivalent Subc
Figure C-11ZERO Flag Logic for Test Instruction
PicoBlaze 8-bit Embedded Microcontroller 117
XOR sX, Operand Logical Bitwise XOR Register sX with Operand
Instruction Codes
Table D-1PicoBlaze Instruction Codes
Jump Z
PicoBlaze 8-bit Embedded Microcontroller 121
Appendix Instruction Codes
Registers
Register and Scratchpad RAM Planning Worksheets
Reg Description
Appendix Register and Scratchpad RAM Planning Worksheets
Scratchpad RAM
Loc Description