PicoBlaze Development Tools, Assembler | Xilinx UG129 manual

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Chapter 9

PicoBlaze Development Tools

There are three primary development environments for creating PicoBlaze™ processor application code, as summarized in Table 9-1. Xilinx offers two PicoBlaze environments. The PicoBlaze reference design includes the KCPSM3 command-line assembler that executes in a Windows DOS box or command window. The Xilinx System Generator for DSP development environment includes both a PicoBlaze assembler and a simulation model for the Math Works MATLAB/Simulink environment. The Mediatronix pBlazIDE software is a graphical development environment including an assembler and full- featured instruction-set simulator (ISS).

Table 9-1:PicoBlaze Development Environments

	Xilinx KCPSM3	Mediatronix pBlazIDE	Xilinx System Generator

Platform Support	Windows	Windows 98, Windows	Windows 2000, Windows
		2000, Windows NT,	XP
		Windows ME, Windows
		XP

Assembler	Command-line in DOS	Graphical	Command-line within
	window		System Generator

Instruction Syntax	KCPSM3	PBlazIDE	KCPSM3

Instruction Set Simulator	Facilities provided for	Graphical/Interactive	Graphical/Interactive
	VHDL simulation

Simulator Breakpoints	N/A	Yes	Yes

Register Viewer	N/A	Yes	Yes

Memory Viewer	N/A	Yes	Yes

KCPSM3

Assembler

The KCPSM3 Assembler is provided as a simple DOS executable file together with three template files. Copy all the files KCPSM3.EXE, ROM_form.vhd, ROM_form.v, and ROM_form.coe into your working directory.

Programs are best written with either the standard Notepad or Wordpad tools available on most Windows computers. However, any PC-format text editor is sufficient. Save the PicoBlaze assembly program with a PSM file extension (eight-character name limit).

PicoBlaze 8-bit Embedded Microcontroller

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UG129 (v1.1.2) June 24, 2008

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Xilinx UG129 manual PicoBlaze Development Tools, Assembler

Contents

UG129 v1.1.2 June 24 PicoBlaze 8-bit Embedded Microcontroller User Guide Version Revision Revision History Limitations Limited Warranty and DisclaimerLimitation of Liability Technical Support Limitations Preface Acknowledgments Acknowledgments About This Guide Guide Contents Preface About This Guide Table of Contents Interrupts Performance Appendix C PicoBlaze Instruction Set and Event Reference Introduction PicoBlaze Microcontroller Features General-Purpose Registers PicoBlaze Microcontroller Functional BlocksInstruction Program Store Introduction Flags Arithmetic Logic Unit ALUByte Scratchpad RAM Input/Output Program Counter PC ResetProgram Flow Control CALL/RETURN Stack Why the PicoBlaze Microcontroller? Why the PicoBlaze Microcontroller?Why Use a Microcontroller within an FPGA? Weaknesses Strengths Signal Direction Description PicoBlaze Interface SignalsPicoBlaze Interface Signal Descriptions Readstrobe 1PicoBlaze Instruction Set alphabetical listing PicoBlaze Instruction Set Enable Interrupt Returni Disable Address Spaces Instruction 1Kx18 Direct PicoBlaze Instruction Set Processing DataLogic Instructions 3Inverting an Individual Bit Location 2Complementing a Register Value Arithmetic Instructions 616-Setting a Bit Location SUB and Subcy Subtract Instructions 10Incrementing and Decrementing a Register Multiplication 148-bit by 8-bit Multiply Routine Produces a 16-bit Product Division 168-bit by 8-bit Multiply Routine Using Hardware Multiplier 18Loading a Register with Itself Acts as a NOP Instruction No Operation NOP Test and Compare Setting and Clearing Carry Flag 22The Test Instruction Affects the Zero Flag Shift and Rotate Instructions 25Generate Parity for a Register Using the Test Instruction 5PicoBlaze Rotate Instructions Rotate Left Rotate Right SRX Program Flow Control Moving Data 6Instruction Conditional Execution Description Program Flow Control CALL/RETURN Program Flow Control UG129 v1.1.2 June 24 1Simple Interrupt Logic Interrupts 2Example Interrupt Flow Example Interrupt Flow Example Interrupt Flow 3Interrupt Timing Diagram Interrupts Address Modes Scratchpad RAMDirect Addressing Indirect Addressing Scratchpad RAM Implementing a Look-Up Table Stack Operations Stack OperationsFifo Operations Scratchpad RAM Portid Port Input and Output Ports 1INPUT Operation and Fpga Interface Logic Input Operations PORTID70 Input OperationsINPORT70 Register s0 Input and Output Ports Applications with Few Input SourcesReadstrobe Interaction with FIFOs Output Operations Output Operations Fpga Register Simple Output Structure for Few Output Destinations 8Use Constant Directives to Declare Output Port Addresses 9Pipelining the Portid Decoding Improves Performance Pipelining for Maximum Performance Pipelining for Maximum Performance Effective Pipelining Improves Read Performance Repartitioning the Design for Maximum Performance Standard Configuration Single 1Kx18 Block RAM Instruction Storage Configurations Two PicoBlaze Microcontrollers Share a 1Kx18 Code Image Instruction Storage Configurations Distributed ROM Instead of Block RAM 6Using Distributed ROM for Instruction Memory Instruction Storage Configurations Input Clock Frequency PerformancePredicting Executing Performance Frequency Performance Assembler PicoBlaze Development Tools PicoBlaze Development Tools Assembly ErrorsInput and Output Files Mediatronix pBlazIDE Configuring pBlazIDE for the PicoBlaze Microcontroller 4Example of How Kcpsm Source Code Converts to pBlazIDE Code Importing KCPSM3 Code into pBlazIDE Directives Differences Between the KCPSM3 Assembler and pBlazIDEDifferences Between the KCPSM3 Assembler and pBlazIDE Function KCPSM3 Directive PBlazIDE Directive PicoBlaze Development Tools KCPSM3 Module Using the PicoBlaze Microcontroller in an Fpga DesignVhdl Design Flow Using the PicoBlaze Microcontroller in an Fpga Design Connecting the Program ROM Generating the Program ROM using progrom.coe Black Box Instantiation of KCPSM3 using KCPSM3.ngcGenerating an ESC Schematic Symbol Black Box Instantiation of KCPSM3 using KCPSM3.ngc Using the PicoBlaze Microcontroller in an Fpga Design Naming or Aliasing Registers Assembler DirectivesLocating Code at a Specific Address Naming the Program ROM Output File Defining ConstantsDefining I/O Ports pBlazIDE PBlazIDE Defining I/O Ports pBlazIDE Input PortsOutput Ports 5Example of pBlazIDE Dsout Directive Input/Output Ports Custom Instruction Op-Codes Custom Instruction Op-Codes Assembler Directives Simulating PicoBlaze Code Instruction Set Simulation with pBlazIDE Instruction Set Simulation with pBlazIDE Simulator Control Buttons2pBlazIDE Simulator Control Buttons Function Assemble Edit Step Over RunRun to Cursor Pause Turbocharging Simulation using FPGAs Turbocharging Simulation using FPGAs Simulating PicoBlaze Code Related Materials and References Chapter Related Materials and References KCPSM3 Syntax Example Program Templates Appendix Example Program Templates PBlazIDE Syntax ADD sX, Operand -Add Operand to Register sX PicoBlaze Instruction Set and Event Reference Appendix PicoBlaze Instruction Set and Event Reference Addcy sX, Operand -Add Operand to Register sX with Carry SX, Operand Logical Bitwise and Register sX with Operand SX, Operand Logical Bitwise and Register sX with Operand Examples Table C-1CALL Instruction Conditions Description Condition Figure C-4COMPARE Operation Compare sX, Operand Compare Operand with Register sX Disable Interrupt Disable External Interrupt Input Disable Interrupt Disable External Interrupt InputEnable Interrupt Enable External Interrupt Input KCPSM3 Instruction PBlazIDE Instruction Figure C-5FETCH Operation Portid Å Operand SX Å Inport PC Å PC + Interrupt Event, When Enabled Table C-2JUMP Instruction Conditions Description Load sX, Operand Load Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Figure C-7OUTPUT Operation and Fpga Interface Logic Table C-3PicoBlaze Reset Values Resource Reset Event Effect Reset EventReset Event Table C-4RETURN Instruction Conditions Description PBlazIDE Equivalent RET, RET C, RET NC, RET Z, RET NZ RR sX Rotate Right Register sX RL sX Rotate Left Register sXTable C-5Rotate Left RL Operation Table C-6Rotate Right RR Operation Table C-7Shift Left Operations SL 0 1 X a sX Shift Left Register sXSL 0 1 X a sX Shift Left Register sX SR 0 1 X a sX Shift Right Register sX Shift Right with ‘ 0’ fill Figure C-8STORE Operation Store sX, sY SUB sX, Operand -Subtract Operand from Register sX Figure C-10SUBCY Instruction Registers sX Flags CARRY, Zero PBlazIDE Equivalent Subc Figure C-11ZERO Flag Logic for Test Instruction PicoBlaze 8-bit Embedded Microcontroller 117 XOR sX, Operand Logical Bitwise XOR Register sX with Operand Table D-1PicoBlaze Instruction Codes Instruction Codes Jump Z PicoBlaze 8-bit Embedded Microcontroller 121 Appendix Instruction Codes Reg Description Register and Scratchpad RAM Planning WorksheetsRegisters Loc Description Scratchpad RAMAppendix Register and Scratchpad RAM Planning Worksheets