22The Test Instruction Affects the Zero Flag | Xilinx UG129 specs

Processing Data

R

Register sY Literal kk

Register sX

7 6 5 4 3 2 1 0

	7					6					5					4					3					2					1

0

Bitwise AND

If all bit results are zero, set ZERO flag.

ZERO

UG129_c3_03_051404

Figure 3-22:The TEST Instruction Affects the ZERO Flag

Each bit of register sX is logically ANDed with either the contents of register sY or a literal constant, kk. The operation sets the ZERO flag if the result of all bitwise AND operations is zero.

If the second operand contains a single ‘1’ bit, then the CARRY flag tests if the corresponding bit in register sX is ‘1’ as shown in the example in Figure 3-23.

LOAD s0,	05	;	s0	= 00000101
TEST s0,	04	;	mask	=	00000100
		; CARRY		=	1, ZERO = 0

Figure 3-23:Generate Parity for a Register Using the TEST Instruction

In a broader application, the CARRY bit generates the odd parity for the included bits in register sX, as shown in Figure 3-24. The second operand acts as a mask. If a bit in the second operand is ‘0’, then the corresponding bit in register sX is not included in the generated parity value. If a bit in the second operand is ‘1’, then the corresponding bit in register sX is included in the final parity value.

Register sY
Register sY	7						6							5						4						3						2						1							0
Literal kk	7						6							5						4						3						2						1							0
Literal kk

Register sX				7							6							5						4					3						2							1

Mask out unwanted bits. 0=mask bit, 1=include bit

0

Generate odd parity (XOR) from bit results.

CARRY

UG129_c3_04_051404

Figure 3-24:The TEST Instruction Affects the CARRY Flag

PicoBlaze 8-bit Embedded Microcontroller

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UG129 (v1.1.2) June 24, 2008

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Xilinx UG129 manual 22The Test Instruction Affects the Zero Flag

Contents

UG129 v1.1.2 June 24 PicoBlaze 8-bit Embedded Microcontroller User Guide Version Revision Revision History Limitations Limited Warranty and DisclaimerLimitation of Liability Technical Support Limitations Preface Acknowledgments Acknowledgments About This Guide Guide Contents Preface About This Guide Table of Contents Interrupts Performance Appendix C PicoBlaze Instruction Set and Event Reference Introduction PicoBlaze Microcontroller Features General-Purpose Registers PicoBlaze Microcontroller Functional BlocksInstruction Program Store Introduction Flags Arithmetic Logic Unit ALUByte Scratchpad RAM Input/Output Program Counter PC ResetProgram Flow Control CALL/RETURN Stack Why the PicoBlaze Microcontroller? Why Use a Microcontroller within an FPGA?Why the PicoBlaze Microcontroller? Weaknesses Strengths PicoBlaze Interface Signals PicoBlaze Interface Signal DescriptionsSignal Direction Description Readstrobe 1PicoBlaze Instruction Set alphabetical listing PicoBlaze Instruction Set Enable Interrupt Returni Disable Address Spaces Instruction 1Kx18 Direct Processing Data Logic InstructionsPicoBlaze Instruction Set 3Inverting an Individual Bit Location 2Complementing a Register Value Arithmetic Instructions 616-Setting a Bit Location SUB and Subcy Subtract Instructions 10Incrementing and Decrementing a Register Multiplication 148-bit by 8-bit Multiply Routine Produces a 16-bit Product Division 168-bit by 8-bit Multiply Routine Using Hardware Multiplier 18Loading a Register with Itself Acts as a NOP Instruction No Operation NOP Test and Compare Setting and Clearing Carry Flag 22The Test Instruction Affects the Zero Flag Shift and Rotate Instructions 25Generate Parity for a Register Using the Test Instruction 5PicoBlaze Rotate Instructions Rotate Left Rotate Right SRX Program Flow Control Moving Data 6Instruction Conditional Execution Description Program Flow Control CALL/RETURN Program Flow Control UG129 v1.1.2 June 24 1Simple Interrupt Logic Interrupts 2Example Interrupt Flow Example Interrupt Flow Example Interrupt Flow 3Interrupt Timing Diagram Interrupts Address Modes Scratchpad RAMDirect Addressing Indirect Addressing Scratchpad RAM Implementing a Look-Up Table Stack Operations Fifo OperationsStack Operations Scratchpad RAM Portid Port Input and Output Ports 1INPUT Operation and Fpga Interface Logic Input Operations PORTID70 Input OperationsINPORT70 Register s0 Applications with Few Input Sources Readstrobe Interaction with FIFOsInput and Output Ports Output Operations Output Operations Fpga Register Simple Output Structure for Few Output Destinations 8Use Constant Directives to Declare Output Port Addresses 9Pipelining the Portid Decoding Improves Performance Pipelining for Maximum Performance Pipelining for Maximum Performance Effective Pipelining Improves Read Performance Repartitioning the Design for Maximum Performance Standard Configuration Single 1Kx18 Block RAM Instruction Storage Configurations Two PicoBlaze Microcontrollers Share a 1Kx18 Code Image Instruction Storage Configurations Distributed ROM Instead of Block RAM 6Using Distributed ROM for Instruction Memory Instruction Storage Configurations Input Clock Frequency PerformancePredicting Executing Performance Frequency Performance Assembler PicoBlaze Development Tools Assembly Errors Input and Output FilesPicoBlaze Development Tools Mediatronix pBlazIDE Configuring pBlazIDE for the PicoBlaze Microcontroller 4Example of How Kcpsm Source Code Converts to pBlazIDE Code Importing KCPSM3 Code into pBlazIDE Directives Differences Between the KCPSM3 Assembler and pBlazIDEDifferences Between the KCPSM3 Assembler and pBlazIDE Function KCPSM3 Directive PBlazIDE Directive PicoBlaze Development Tools Using the PicoBlaze Microcontroller in an Fpga Design Vhdl Design FlowKCPSM3 Module Using the PicoBlaze Microcontroller in an Fpga Design Connecting the Program ROM Generating the Program ROM using progrom.coe Black Box Instantiation of KCPSM3 using KCPSM3.ngcGenerating an ESC Schematic Symbol Black Box Instantiation of KCPSM3 using KCPSM3.ngc Using the PicoBlaze Microcontroller in an Fpga Design Assembler Directives Locating Code at a Specific AddressNaming or Aliasing Registers Naming the Program ROM Output File Defining ConstantsDefining I/O Ports pBlazIDE PBlazIDE Input Ports Output PortsDefining I/O Ports pBlazIDE 5Example of pBlazIDE Dsout Directive Input/Output Ports Custom Instruction Op-Codes Custom Instruction Op-Codes Assembler Directives Simulating PicoBlaze Code Instruction Set Simulation with pBlazIDE Instruction Set Simulation with pBlazIDE Simulator Control Buttons2pBlazIDE Simulator Control Buttons Function Assemble Edit Step Over RunRun to Cursor Pause Turbocharging Simulation using FPGAs Turbocharging Simulation using FPGAs Simulating PicoBlaze Code Related Materials and References Chapter Related Materials and References KCPSM3 Syntax Example Program Templates Appendix Example Program Templates PBlazIDE Syntax ADD sX, Operand -Add Operand to Register sX PicoBlaze Instruction Set and Event Reference Appendix PicoBlaze Instruction Set and Event Reference Addcy sX, Operand -Add Operand to Register sX with Carry SX, Operand Logical Bitwise and Register sX with Operand SX, Operand Logical Bitwise and Register sX with Operand Examples Table C-1CALL Instruction Conditions Description Condition Figure C-4COMPARE Operation Compare sX, Operand Compare Operand with Register sX Disable Interrupt Disable External Interrupt Input Enable Interrupt Enable External Interrupt InputDisable Interrupt Disable External Interrupt Input KCPSM3 Instruction PBlazIDE Instruction Figure C-5FETCH Operation Portid Å Operand SX Å Inport PC Å PC + Interrupt Event, When Enabled Table C-2JUMP Instruction Conditions Description Load sX, Operand Load Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Or sX, Operand Logical Bitwise or Register sX with Operand Figure C-7OUTPUT Operation and Fpga Interface Logic Reset Event Reset EventTable C-3PicoBlaze Reset Values Resource Reset Event Effect Table C-4RETURN Instruction Conditions Description PBlazIDE Equivalent RET, RET C, RET NC, RET Z, RET NZ RR sX Rotate Right Register sX RL sX Rotate Left Register sXTable C-5Rotate Left RL Operation Table C-6Rotate Right RR Operation SL 0 1 X a sX Shift Left Register sX SL 0 1 X a sX Shift Left Register sXTable C-7Shift Left Operations SR 0 1 X a sX Shift Right Register sX Shift Right with ‘ 0’ fill Figure C-8STORE Operation Store sX, sY SUB sX, Operand -Subtract Operand from Register sX Figure C-10SUBCY Instruction Registers sX Flags CARRY, Zero PBlazIDE Equivalent Subc Figure C-11ZERO Flag Logic for Test Instruction PicoBlaze 8-bit Embedded Microcontroller 117 XOR sX, Operand Logical Bitwise XOR Register sX with Operand Table D-1PicoBlaze Instruction Codes Instruction Codes Jump Z PicoBlaze 8-bit Embedded Microcontroller 121 Appendix Instruction Codes Register and Scratchpad RAM Planning Worksheets RegistersReg Description Scratchpad RAM Appendix Register and Scratchpad RAM Planning WorksheetsLoc Description