Texas Instruments VLYNQ Port manual

Contents

Main Page Contents Page Page Page Preface Read This First About This Document Notational Conventions Related Documentation From Texas Instruments Page 1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide VLYNQ Port 1.3 Functional Block Diagram 1.4 Industry Standard(s) Compliance Statement 2 Peripheral Architecture 2.1 Clock Control Page 2.5 VLYNQ Functional Description (FIFO3) (FIFO2) (FIFO0) (FIFO1) SPRUE36A September 2007 VLYNQ Port 13Submit Documentation Feedback 2.5.1 Write Operations VLYNQ Port14 SPRUE36A September 2007Submit Documentation Feedback 2.5.2 Read Operations SPRUE36A September 2007 VLYNQ Port 15Submit Documentation Feedback 2.6 Initialization 2.7 Auto-Negotiation 2.8 Serial Interface Width Configuration 2.9 Address Translation Figure 7. Example Address Memory Map Page 2.10 Flow Control 2.11 Reset Considerations 2.12 Interrupt Support 2.12.2 Writes to Interrupt Pending/Set Register INTLOCAL=1 INTLOCAL=0 Figure 8. Interrupt Generation Mechanism Block Diagram 2.13 DMA Event Support 2.14 Power Management 2.15 Emulation Considerations 3 VLYNQ Port Registers 3.1 Revision Register (REVID) Table 7. Revision Register (REVID) Field Descriptions 3.2 Control Register (CTRL) Table 8. Control Register (CTRL) Field Descriptions Table 8. Control Register (CTRL) Field Descriptions (continued) 3.3 Status Register (STAT) Table 9. Status Register (STAT) Field Descriptions Table 9. Status Register (STAT) Field Descriptions (continued) 3.4 Interrupt Priority Vector Status/Clear Register (INTPRI) 3.5 Interrupt Status/Clear Register (INTSTATCLR) 3.6 Interrupt Pending/Set Register (INTPENDSET) 3.7 Interrupt Pointer Register (INTPTR) 3.8 Transmit Address Map Register (XAM) 3.9 Receive Address Map Size 1 Register (RAMS1) 3.10 Receive Address Map Offset 1 Register (RAMO1) 3.11 Receive Address Map Size 2 Register (RAMS2) 3.12 Receive Address Map Offset 2 Register (RAMO2) 3.13 Receive Address Map Size 3 Register (RAMS3) 3.14 Receive Address Map Offset 3 Register (RAMO3) 3.15 Receive Address Map Size 4 Register (RAMS4) 3.16 Receive Address Map Offset 4 Register (RAMO4) 3.17 Chip Version Register (CHIPVER) 3.18 Auto Negotiation Register (AUTNGO) Figure 25. Chip Version Register (CHIPVER) Table 23. Chip Version Register (CHIPVER) Field Descriptions Table 24. Auto Negotiation Register (AUTNGO) Field Descriptions 4 Remote Configuration Registers Remote Configuration Registers Table 25. VLYNQ Port Remote Controller Registers Appendix A VLYNQ Protocol Specifications A.1 Special 8b/10b Code Groups A.2 Supported Ordered Sets Appendix A Table A-1. Special 8b/10b Code Groups A.3 VLYNQ 2.0 Packet Format VLYNQ 2.0 Packet Format Table A-3. Packet Format (10-bit Symbol Representation) Description A.4 VLYNQ 2.X Packets VLYNQ 2.X Packets Page Appendix B Write/Read Performance B.1 Write Performance Write Performance Table B-1. Scaling Factors Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) B.2 Read Performance Appendix C Revision History Appendix C IMPORTANT NOTICE