Vlynq 2.X Packets | Texas Instruments VLYNQ Port specs

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VLYNQ 2.X Packets

A.4 VLYNQ 2.X Packets

An example of what can happen to a write burst due to remote and local FIFO state changes and the link pulse timer expiring is shown in Example A-1. This protocol can be extended to apply to multiple channels; therefore, the data return channel is logically isolated from the command channel.

Example A-1. A write burst due to remote and local FIFO state changes and the link pulse timer expiring

Basic packets:

Read32 - caaaaT

Write32 - caaaaddddT

ReadCfg - claaaaT

WriteCfg - claaaaddddddddT

ReadBurst - claaaaT

WriteBurst - claaaaddddddddddddT

Int - cddddT

ReadReturn - clddddddddT

Where

I - Idle

T - EndOfPacket

d - data

a - address

c - command

l - length

M - Byte mask

I[#] - Flowed, # is used when exiting flowed for a channel, the # is actually the current channel command.

P# - Flow Enable for a channel

C# - Flow Disable for a channel L - Link pulse

and what is in italics is optional data up to 16 words total. Packet with byte enables:

WriteBurst - claaaaMMddMMddMMddT

The above packet wrote to the LS half words from the specified address. Packet that has been flowed due to remote FIFO status:

WriteBurst - claaaaMMddMIIIIIIIIIIIII#MddMMddT

The packet was extended using the I code. The # is used to indicate that the same channel was continued.

To the same packet, the potential flowing of the local FIFO’s is added: WriteBurst - claaaaMMddMIIP#IIIIIIIIIIIII#MddMMdC#dT

Link pulse to the stream is added:

WriteBurst - claaLaaMMddMIIP#IIIIIIIIIII#MddMMdC#dT

An example of a write burst flowed and interrupted by a read return data burst is shown below. In the example, a 1 indicates a data return channel (it is actually the return data command) and a 0 indicates a command channel, which is the command for the transaction.

IIIIclaaaaddddIcldddIII1ddddII0dddddddddddddIIIIII0dddTIIIII1dTIIII

SPRUE36A –September 2007

VLYNQ Protocol Specifications

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Texas Instruments VLYNQ Port manual Vlynq 2.X Packets

Contents

Users Guide Submit Documentation Feedback Contents Appendix C Appendix B List of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block Diagram Clock Control Peripheral Architecture Protocol Description Signal DescriptionsVlynq Port Pins Pin Multiplexing Vlynq Module Structure Vlynq Functional Description TxSM Write Operations Read Operations Serial Interface Width Serial Interface Width ConfigurationInitialization Auto-Negotiation Address Translation Register DM644x Vlynq Module Address Translation Example Single Mapped Region Remote Vlynq Module DM644x Vlynq Module Example 1. Address Translation Example Flow Control Interrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations Writes to Interrupt Pending/Set Register Interrupt Generation Mechanism Block Diagram DMA Event Support Serial Bus Error InterruptsRemote Interrupts Emulation Considerations Power Management Block Name Start Address End Address Size Vlynq Port RegistersVlynq Register Address Space Vlynq Port Controller Registers Bit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj Revmin Control Register Ctrl Field Descriptions Control Register Ctrl Bit Field Aoptdisable Status Register Stat Field Descriptions Status Register Stat Lerror No error Instat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr Nointpend Intset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field Descriptions Address Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1 RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2 RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3 RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4 Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field Descriptions Vlynq Port Remote Controller Registers Remote Configuration Registers Table A-1. Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Supported Ordered Sets Vlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol Representation Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read Performance Bit Words Mbits/sec Mbytes/sec Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Burst Size Interface Running at 76.5 MHZ Table B-3. Relative Performance with Various Latencies Read Performance Table C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid