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Texas Instruments VLYNQ Port manual Signal Descriptions, Pin Multiplexing, Protocol Description

Models: VLYNQ Port

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2.2Signal Descriptions

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Peripheral Architecture

2.2Signal Descriptions

The VLYNQ module on the DM644x device is configurable for a 1 to 4 bit-wide RX/TX. Chip-level pin multiplexing registers control the configuration. See the pin multiplexing information in the device-specific data manual.

If the configured width does not match the number of transmit/receive lines that are available on the remote device, negotiation between the two VLYNQ devices automatically configures the width (see Section 2.7).

The VLYNQ interface signals are shown in Table 1.

Pin Name	Signal Name
VLYNQ_CLOCK	VLYNQ serial clock
VLYNQ_SCRUN	VLYNQ serial clock
	run request
	(Active low)

VLYNQ_RXD[0:3] VLYNQ receive data VLYNQ_TXD[0:3] VLYNQ transmit data

	Table 1. VLYNQ Port Pins
I/O	Description
I/O	The VLYNQ reference clock supports the internally or externally generated
	clock.
I/O	The VLYNQ serial clock run request allows remote requests for the VLYNQ
	serial clock to be turned off for system power management.
	Low: The request VLYNQ serial clock is active.
	High: The VLYNQ serial clock is requested to be high when all transactions are
	complete.
I	VLYNQ receive data is synchronous with the VLYNQ serial clock.
O	VLYNQ transmit data is synchronous with the VLYNQ serial clock.

2.3Pin Multiplexing

The VLYNQ signals share pins on the processor package with other processor functions. The VLYNQ module pins are not enabled at reset. In order to change the default function of device pins at reset, the pin multiplexing registers (PINMUXn) must be configured appropriately. See the pin multiplexing information in the device-specific data manual for more detailed information on the processor pin multiplexing and configuration registers.

2.4Protocol Description

VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packet delineation and control.

Appendix A provides general information on 8b/10b coding definitions and their implementation within the VLYNQ module in the DM644x device.

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VLYNQ Port

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Texas Instruments manual Signal Descriptions, Pin Multiplexing, Protocol Description, VLYNQ Port Pins

Contents

Users Guide TMS320DM644x DMSoC VLYNQ PortSPRUE36A -September Submit Documentation FeedbackContents Contents Supported Ordered SetsVLYNQ 2.0 Packet Format VLYNQ 2.X PacketsList of Figures List of Tables List of TablesRead This First PrefaceAbout This Document Notational ConventionsTrademarks VLYNQ is a trademark of Texas InstrumentsVLYNQ Port Users Guide1.2 Features 1 Introduction1.3 Functional Block Diagram Figure 1. VLYNQ Port Functional Block Diagram1.4 Industry Standards Compliance Statement Figure 2. External Clock Block Diagram Figure 3. Internal Clock Block Diagram2 Peripheral Architecture 2.1 Clock Control2.2 Signal Descriptions Table 1. VLYNQ Port Pins2.3 Pin Multiplexing 2.4 Protocol Description2.5 VLYNQ Functional Description Figure 4. VLYNQ Module Structure2.5.1 Write Operations Figure 5. Write Operations2.5.2 Read Operations Figure 6. Read Operations2.8 Serial Interface Width Configuration 2.6 Initialization2.7 Auto-Negotiation Table 2. Serial Interface Width2.9 Address Translation Figure 7. Example Address Memory Map Table 3. Address Translation Example Single Mapped RegionDM644x VLYNQ Module Remote VLYNQ ModuleTable 4. Address Translation Example Single Mapped Region Remote VLYNQ Module2.10 Flow Control Example 1. Address Translation ExampleSee Appendix A 2.11 Reset Considerations 2.11.1 Software Reset Considerations2.11.2 Hardware Reset Considerations 2.12 Interrupt SupportFigure 8. Interrupt Generation Mechanism Block Diagram 2.12.2 Writes to Interrupt Pending/Set Register2.12.4 Serial Bus Error Interrupts 2.13 DMA Event Support2.12.3 Remote Interrupts 2.14 Power Management 2.15 Emulation Considerations3 VLYNQ Port Registers Table 5. VLYNQ Register Address SpaceTable 6. VLYNQ Port Controller Registers 3.1 Revision Register REVID Figure 9. Revision Register REVIDTable 7. Revision Register REVID Field Descriptions VLYNQ Port Registers3.2 Control Register CTRL Figure 10. Control Register CTRLTable 8. Control Register CTRL Field Descriptions VLYNQ Port RegistersTable 8. Control Register CTRL Field Descriptions continued VLYNQ Port RegistersField Description3.3 Status Register STAT Figure 11. Status Register STATTable 9. Status Register STAT Field Descriptions VLYNQ Port RegistersTable 9. Status Register STAT Field Descriptions continued VLYNQ Port RegistersField Description3.4 Interrupt Priority Vector Status/Clear Register INTPRI 3.5 Interrupt Status/Clear Register INTSTATCLRFigure 12. Interrupt Priority Vector Status/Clear Register INTPRI Figure 13. Interrupt Status/Clear Register INTSTATCLR3.6 Interrupt Pending/Set Register INTPENDSET 3.7 Interrupt Pointer Register INTPTRFigure 14. Interrupt Pending/Set Register INTPENDSET Figure 15. Interrupt Pointer Register INTPTR3.8 Transmit Address Map Register XAM Figure 16. Transmit Address Map Register XAMTable 14. Address Map Register XAM Field Descriptions VLYNQ Port Registers3.9 Receive Address Map Size 1 Register RAMS1 3.10 Receive Address Map Offset 1 Register RAMO1Figure 17. Receive Address Map Size 1 Register RAMS1 Figure 18. Receive Address Map Offset 1 Register RAMO13.11 Receive Address Map Size 2 Register RAMS2 3.12 Receive Address Map Offset 2 Register RAMO2Figure 19. Receive Address Map Size 2 Register RAMS2 Figure 20. Receive Address Map Offset 2 Register RAMO23.13 Receive Address Map Size 3 Register RAMS3 3.14 Receive Address Map Offset 3 Register RAMO3Figure 21. Receive Address Map Size 3 Register RAMS3 Figure 22. Receive Address Map Offset 3 Register RAMO33.15 Receive Address Map Size 4 Register RAMS4 3.16 Receive Address Map Offset 4 Register RAMO4Figure 23. Receive Address Map Size 4 Register RAMS4 Figure 24. Receive Address Map Offset 4 Register RAMO43.17 Chip Version Register CHIPVER 3.18 Auto Negotiation Register AUTNGOFigure 25. Chip Version Register CHIPVER Table 23. Chip Version Register CHIPVER Field Descriptions4 Remote Configuration Registers Table 25. VLYNQ Port Remote Controller RegistersRemote Configuration Registers Appendix A VLYNQ Protocol Specifications A.1 Special 8b/10b Code GroupsA.2 Supported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation A.3 VLYNQ 2.0 Packet FormatTable A-3. Packet Format 10-bit Symbol Representation Description A.4 VLYNQ 2.X Packets VLYNQ 2.X PacketsA command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor the command for return data actually indicates a channel 1, and the channel 1 packet is now under way. A flow is now received for channel 1, but it is soon disabled so the channel 1 packet continues. The flow is enabled for channel one again, quickly after flow is released for channel 0, so the data continues for channel 0 when a flow is received again for channel 0. Channel 0 then receives a flow disable, completes its packet, followed by channel 1 flow disable, where the channel 1 packet is also completed Appendix B Write/Read Performance B.1 Write PerformanceTable B-1. Scaling Factors Write PerformanceBurst Size in 32-bit words Data BytesB.2 Read Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAppendix C Additions/Modifications/Deletionspower.ti.com IMPORTANT NOTICEProducts Applications